MCS-40^TM PROGRAM MEMORY ORGANIZATION

MCS-40 program memory is normally located in a Read Only Memory (ROM) such as a 4001 ROM or a 4308 ROM. By the use of interface components such as the 4289 Standard Memory Interface, MCS-40 program memory can be in a PROM memory (Programmable Read Only Memory) such as a 4702A PROM component or a RAM memory such as a 4101 RAM component. Program memory is always organized as an 8-bit wide memory array.
MCS-40 program memory is also conceptually divided into 256-byte pages. A page of memory is by definition a group of 256 bytes where the high-order 4 bits of the 12-bit address are the same. For 4001 ROMs, which are 256 x 8 memory components, a page is physically contained in one ROM chip. Certain MCS-40 instruction address data or other instructions only whithin the page in which the instruction itself is located. In other words, the 12-bit address of data or another instruction is formed by combining the 4 high-order bits from the program counter (the current page number) with the remaining 8 bits of address provided by the instruction.


INSTRUCTION SET

The 4040 is functionally compatible with the 4004 and therefore recognizes all 46 instructions valid for the 4004. In addition, the 4040 recognizes 14 new instructions giving a total of 60 instructions in the set. The instruction format is, of course, identical to that used in the 4004.
Four groups of instructions can be defined as follows:

a.	Machine Instructions - This group of 16 instructions are designated by an OPR code of 0000 - 1101. Within this group is contained a second group which is desinated supplemental group.
b.	4040 Group - This group of 14 instructions is designated by an OPR code of 0000 and an OPA code of 0001 - 1110. These are the new instructions which have been added to the 4040.
c.	I/O Group - Designated by an OPR code of 1110, this group of 16 instructions is used for transferring data between the processor and the RAM chips of I/O circuits.
d.	Accumulator group - This group of 14 instructions is designated by an OPR code of 1111 and operates only on the accumulator/carry flip-flop, the special ROMs and the command register.

Instruction Set Format

Machine instructions

-	1-word instructions - 8 bits wide and requiring 8 clock periods (1 instruction cycle) for execution
-	2-word instructions - 16 bits wide and requiring 16 clock periods (2 instruction cycles) for execution

A 1-word instruction occupies one location in ROM (each location can hold one 8 bit word) and 2-word instruction occupies two successive locations in ROM. Each instruction word is divided into two 4 bit nibbles. The upper 4 bit is called the OPR and contains the operation code. The lower 4 bits is called OPA and contains the modifier. For a single word machine instruction the operation code (OPR) contains the code of the operation that is to be performed (add, subtract, load, etc.). The modifie (OPA) contains one of 4 things:

1.	A register address
2.	A register pair address
3.	4 bits of data
4.	An instruction modifier

For a 2-word machine instruction the first word is similar to a 1-word instruction, however, the modifier (OPA) contains one of 4 things:

1.	A register address
2.	A register pair address
3.	The upper portion of another ROM address
4.	A condition for jumping

The 2nd word contains either the middle portion (in OPR) and lower portion (in OPA) of another ROM address or 8 bits of data (the upper 4 bits in OPR and the lower 4 bits in OPA).
The upper 4 bits of instruction (OPR) will always be fetched before the lower 4 bits of instruction (OPA) during M₁ and M₂ respectively.

Input/Output & RAM instructions and Accumulator Group Instructions
In these instructions (which are all single word) the OPR contains a 4 bit code which identifies either the I/O instruction or the accumulator group instruction and the OPA contains a 4 bit code which identifies the operation to be performed.

Index register organization

The index register can be addressed in two modes at any one time:

a.	By specifying 1 out of 16 possible locations with an OPA code of the form RRRR(1). The bank switch of the 4040 can access an additional 8.
b.	By specifying 1 out of 8 pairs (12 pairs on 4040) with an OPA code of the form RRRX(2).

When the index register is used as a pair register, the even number register (RRR0) is used as the location of the middle address or the upper data fetched from the ROM, the odd number register (RRR1) is used as the location of the lower address or the lower data fetched from the ROM.

Note 1: In this case, the instruction is executed on the 4-bit content addressed by RRRR.
Note 2: In this case, the instruction is executed on the 8-bit content addressed by RRRX, where X is 0 or 1 depending on the instruction.

Operation of the Address Register (Program Counter and Stack)

The address register contains four 12 bit register for the 4004 and eight 12 bit register for the 4040; one register is used as the program counter and stores the instruction address; the other registers make up the push down stack.
Initially, any one of the address registers can be used as the program counter to store the instruction address. In a typical sequence, the program counter is incremented by 1 after the last address is sent out. This new address then becomes the effective address. If a JMS (Jump to Subroutine) instruction is received by the CPU, the program control is transferred to the address called out in JMS intruction. This address is stored in the register just above the old program counter which now saves the address of the next instruction to be executed following the last JMS⁽¹⁾. This return address becomes the effective address following the BBL (Branch Back and Load) instruction at the end of the subroutine. The 4040 CPU can in addition to executing JMS/BBL combination to get to and from a subroutine, can also execute an interrupt/BBS. In this case, the interrupt forces the program to location 003. The BBS returns the program counter to its previous value plus 1 and sends out the value stored in the SRC Save Register to restore port selection logic to the state that existed before the interrupt.
In summary, then, a JMS intruction pushes the program counter up one level and a BBL instruction pushes the program counter down one level. Since there are 7 registers in the push down stack of the 4040, 7 return addresses may be saved. If an eighth JMS occurs, the deepest return address (the first one stored) is lost. FOr a 4004, a fourth JMS occurence without an intermediate return causes the loss of one return address. (see Figure 1-17 below).

Note 1: Since the JMS instruction is a 2-word instruction the old effective address is incremented by 2 to correctly give the address of the next instruction to be executed after the return from JMS.



INSTRUCTION SET SUMMARY

The instruction set of the 4040 and 4004 (CPU) are shown below. The following section will describe each instruction in detail.
[Those instructions preceded by an asterisk (*) are 2 word instructions that occupy 2 successive locations in ROM]


MACHINE INSTRUCTIONS (Logic 1 = Low Voltage = Negative Voltage (V_DD); Logic 0 = High Voltage = (V_SS)

MNEMONIC	OPR D3 D2 D1 D0	OPA D3 D2 D1 D0	DESCRIPTION OF OPERATION
NOP	0 0 0 0	0 0 0 0	No operation.
*JCN	0 0 0 1 A2 A2 A2 A2	C1 C2 C3 C4 A1 A1 A1 A1	Jump to ROM address A2A2A2A2 A1A1A1A1 (within the same ROM that contains this JCN instruction) if condition C1C2C3C4(1) is true, otherwise skip (go to the next instruction in sequence).
*FIM	0 0 1 0 D2 D2 D2 D2	R1 R2 R3 04 D1 D1 D1 D1	Fetch immediate (direct) form ROM Data D2D2D2D2 D1D1D1D1 to index register pair location RRR.(2)
SRC	0 0 1 0	R R R 1	Send register control. Send the address (contents of index register pair RRR) to ROM and RAM at X2 and X3 time in the Instruction Cycle.
FIN	0 0 1 1	R R R 0	Fetch indirect from ROM. Send contents of index register pair location 0 out as an address. Data fetched is placed into register pair location RRR.
JIN	0 0 1 1	R R R 1	Jump indirect. Send contents of register pair RRR out as an address at A1 and A2 time in the Instruction Cycle.
*JUN	0 1 0 0 A2 A2 A2 A2	A3 A3 A3 A3 A1 A1 A1 A1	Jump unconditional to ROM address A3A3A3A3 A2A2A2A2 A1A1A1A1.
*JMS	0 1 0 1 A2 A2 A2 A2	A3 A3 A3 A3 A1 A1 A1 A1	Jump to subroutine ROM address A3A3A3A3 A2A2A2A2 A1A1A1A1, save old address. (Up 1 level in stack)
INC	0 1 1 0	R R R R	Increment contents of register RRRR.(3)
*ISZ	0 1 1 1 A2 A2 A2 A2	R R R R A1 A1 A1 A1	Increment contents of register RRRR. Go to ROM address A2A2A2A2 A1A1A1A1 (within the same ROM that contains this ISZ instruction) if result is not 0, otherwise skip (go to the next instruction in sequence).
ADD	1 0 0 0	R R R R	Add contents of register RRRR to accumulator with carry.
SUB	1 0 0 1	R R R R	Subtract contents of register RRRR from accumulator with borrow.
LD	1 0 1 0	R R R R	Load contents of register RRRR to accumulator.
XCH	1 0 1 1	R R R R	Exchange contents of index register RRRR and accumulator.
BBL	1 1 0 0	D D D D	Branch back (down 1 level in stack) and load data DDDD to accumulator.
LDM	1 1 0 1	D D D D	Load data DDDD to accumulator.

ACCUMULATOR GROUP INSTRUCTIONS

MNEMONIC	OPR D3 D2 D1 D0	OPA D3 D2 D1 D0	DESCRIPTION OF OPERATION
CLB	1 1 1 1	0 0 0 0	Clear both. (Accumulator and carry)
CLC	1 1 1 1	0 0 0 1	Clear carry
IAC	1 1 1 1	0 0 1 0	Increment accumulator.
CMC	1 1 1 1	0 0 1 1	Complement carry.
CMA	1 1 1 1	0 1 0 0	Complement accumulator.
RAL	1 1 1 1	0 1 0 1	Rotate left. (Accumulator and carry)
RAR	1 1 1 1	0 1 1 0	Rotate right. (Accumulator and carry)
TCC	1 1 1 1	0 1 1 1	Transmit carry to accumulator and clear carry.
DAC	1 1 1 1	1 0 0 0	Decrement accumulator.
TCS	1 1 1 1	1 0 0 1	Transfer carry subtract and clear carry.
STC	1 1 1 1	1 0 1 0	Set carry.
DAA	1 1 1 1	1 0 1 1	Decimal adjust accumulator.
KBP	1 1 1 1	1 1 0 0	Keyboard process. Converts the contents of the accumulator from a one out of four code to a binary code.
DCL	1 1 1 1	1 1 0 1	Designate command line.

INPUT/OUTPUT AND RAM INSTRUCTIONS for the following devices: 4001, 4002, 4008, 4009 and 4289*
(The RAM's and ROM's operated on in the I/O and RAM instructions have been previously selected by the last SRC instuction executed.)

MNEMONIC	OPR D3 D2 D1 D0	OPA D3 D2 D1 D0	DESCRIPTION OF OPERATION
WRM	1 1 1 0	0 0 0 0	Write the contents of the accumulator into the previously selected RAM main memory character.
WMP	1 1 1 0	0 0 0 1	Write the contents of the accumulator into the previously selected RAM output port.
WRR	1 1 1 0	0 0 1 0	Write the contents of the accumulator into the previously selected ROM output port. (I/O Lines)
WPM	1 1 1 0	0 0 1 1	Write the contents of the accumulator into the previously selected half byte of read/write program memory (for use with 4008/4009 or 4289).
WR0(4)	1 1 1 0	0 1 0 0	Write the contents of the accumulator into the previously selected RAM status character 0.
WR1(4)	1 1 1 0	0 1 0 1	Write the contents of the accumulator into the previously selected RAM status character 1.
WR2(4)	1 1 1 0	0 1 1 0	Write the contents of the accumulator into the previously selected RAM status character 2.
WR3(4)	1 1 1 0	0 1 1 1	Write the contents of the accumulator into the previously selected RAM status character 3.
SBM	1 1 1 0	1 0 0 0	Subtract the previously selected RAM main memory character from the accumulator with borrow.
RDM	1 1 1 0	1 0 0 1	Read the previously selected RAM main memory character into the accumulator.
RDR	1 1 1 0	1 0 1 0	Read the contents of the previously selected ROM input port int the accumulator. (I/O Lines)
ADM	1 1 1 0	1 0 1 1	Add the previously selected RAM main memory character to the accumulator with carry.
RD0(4)	1 1 1 0	1 1 0 0	Read the previously selected RAM status character 0 into the accumulator.
RD1(4)	1 1 1 0	1 1 0 1	Read the previously selected RAM status character 1 into the accumulator.
RD2(4)	1 1 1 0	1 1 1 0	Read the previously selected RAM status character 2 into the accumulator.
RD3(4)	1 1 1 0	1 1 1 1	Read the previously selected RAM status character 3 into the accumulator.

^*For explanation of 4625 and 4269 I/O instructions, see the 4265 and 4269 data sheets.

4040 ONLY INSTRUCTIONS

MNEMONIC	OPR D3 D2 D1 D0	OPA D3 D2 D1 D0	DESCRIPTION OF OPERATION
HLT	0 0 0 0	0 0 0 1	Halt - inhibit program counter and data buffers.
BBS	0 0 0 0	0 0 1 0	Branch Back from Interrupt and restore the previous SRC. The program counter and send register control are restored to their pre-interrupt value.
LCR	0 0 0 0	0 0 1 1	The contents of the COMMAND REGISTER are transferred to the accumulator.
OR4	0 0 0 0	0 1 0 0	The 4 bit contents of index register #4 are logically "OR-ed" with the accumulator.
OR5	0 0 0 0	0 1 0 1	The 4 bit contents of index register #5 are logically "OR-ed" with the accumulator.
AN6	0 0 0 0	0 1 1 0	The 4 bit contents of index register #6 are logically "AND-ed" with the accumulator.
AN7	0 0 0 0	0 1 1 1	The 4 bit contents of index register #7 are logically "AND-ed" with the accumulator.
DB0	0 0 0 0	1 0 0 0	DESIGNATE ROM BANK 0. CM-ROM0 becomes enabled.
DB1	0 0 0 0	1 0 0 1	DESIGNATE ROM BANK 1. CM-ROM1 becomes enabled.
SB0	0 0 0 0	1 0 1 0	SELECT INDEX REGISTER BANK 0. The index registers 0 - 7.
SB1	0 0 0 0	1 0 1 1	SELECT INDEX REGISTER BANK 1. The index registers 0* - 7*.
EIN	0 0 0 0	1 1 0 0	ENABLE INTERRUPT.
DIN	0 0 0 0	1 1 0 1	DISABLE INTERRUPT.
RPM	0 0 0 0	1 1 1 0	READ PROGRAM MEMORY.

NOTES:	(1)The condition code is assigned as follows:          C1 = 1    Invert jump condition          C2 = 1    Jump if accumulator is zero          C4 = 1    Jump if test signal is a 0          C1 = 0    Not invert jump condition          C3 = 1    Jump if carry/link is a 1
	(2)RRR is the address of 1 of 8 index register pairs in the CPU.
	(3)RRRR is the address of 1 of 16 index registers in the CPU.
	(4)Each RAM chip has 4 registers, each with twenty 4-bit characters subdivided into 16 main memory characters and 4 status characters. Chip number, RAM register and main memory character are addressed by an SRC instruction. For the selected chip and register, however, status character locations are selected by the instruction code (OPA).

DETAILED INSTRUCTION DESCRIPTION

A.	Symbols and Abbreviations
	The following symbols and abbreviations will be used throughout the next few sections:      SRCR      SRC Register () the content of → is transferred to ACC Accumulator (4 bit) CY Carry Flip-Flop ACBR Accumulator Buffer Register (4 bit) RRRR Index register address RRR Index register pair address PL Low order program counter Field (4 bit) PM Middle order program counter Field (4 bit) PH High order program counter Field (4 bit) ai Order i content of the accumulator CMi Order i content of the command register M RAM main character location Msi RAM status character i DB (T)si Data bus content at time T Stacksi The 3 (for 4004) of 7 (for 4040) registers in the address register other than the program counter CRsi Command register IEsi Interrupt enable RB0si Register bank 0 RRRR0 - RRRR7, enable RB1si Register bank 1 RRRR0* - RRRR7*, enable  | Logical OR & Logical AND Throughout the text "page" means a block of 256 instructions whose address differs only on the least significant 8 bits; e.g., page 7 means all locations having addresses between 0111 0000 0000 and 0111 1111 1111.
B.	Format for Describing Each Instruction
	Each instruction will be described as follows: (1)   Mnemonic symbol and meaning (2)   OPR and OPA code (3)   Symbolic representation of the instruction (4)   Description of the instruction (if necessary) (5)   Example and/or exceptions (if necessary)
C.	One Word Machine Instructions
	Mnemonic:   NOP (No Operation) OPR OPA: 0000 0000 Symbolic: Not applicable Description: No operation performed.
	Mnemonic:   LDM (Load Data to Accumulator) OPR OPA: 1101 DDDD Symbolic: DDDD → ACC Description: The 4 bits of data, DDDD stored in the OPA field of instruction word are loaded into the accumulator. The previous contents of the accumulator are lost. The carry/link bit is unaffected.
	Mnemonic:   LD (Load index register to Accumulator) OPR OPA: 1010 RRRR Symbolic: (RRRR) → ACC Description: The 4 bit content of the designated index register (RRRR) is loaded into the accumulator. The previous contents of the accumulator are lost. The 4 bit content of the index register and the carry/link bit are unaffected.
	Mnemonic:   XCH (Exchange index register and accumulator) OPR OPA: 1011 RRRR Symbolic: (ACC) → ACBR, (RRRR) → ACC, (ACBR) → RRRR Description: The 4 bit content of the designated index register is loaded into the accumulator. The prior content of the accumulator is loaded into the designated register. The carry/link bit is unaffected.
	Mnemonic:   ADD (Add index register to accumulator with carry) OPR OPA: 1000 RRRR Symbolic: (RRRR) + (ACC) + (CY) → ACC, CY Description: The 4 bit content of the designated index register is added to the content of the accumulator with carry. The result is stored in the accumulator. The carry/link is set to 1 if a sum greater than 1510 was generated to indicate a carry out; otherwise, the carry/link is set to 0. The 4 bit content of the index register is unaffected. Example:     a3a2a1a0   ← (ACC)   Augend   + c0   ← (CY)       + r3r2r1r0   ← (RRRR)   Addend   Carry →  c4 s3s2s1s0   ← ACC   SUM
	Mnemonic:   SUB (Subtract index register from accumulator with borrow) OPR OPA: 1001 RRRR Symbolic: (ACC) + (RRRR) + (CY) → ACC, CY Description: The 4 bit content of the designated index register is complemented (ones complement) and added to content of the accumulator with borrow and the result is stored in the accumulator. If a borrow is generated, the carry bit is set to 0; otherwise, it is set to 1. The 4 bit content of the index register is unaffected. Example:     a3a2a1a0   ← (ACC)   Minuend   +        c0   ← (CY)       + r3r2r1r0   ← (RRRR)   Subtrahend   Borrow →  c4 s3s2s1s0   ← ACC   Result
	Mnemonic:   INC (Increment index register) OPR OPA: 0110 RRRR Symbolic: (RRRR) + 1 → RRRR Description: The 4 bit content of the designated index register is incremented by 1. The index register is set to zero in case of overflow. The carry/link is unaffected.
	Mnemonic:   BBL (Branch back and load data to the accumulator) OPR OPA: 1100 DDDD Symbolic: (Stack) → PLPMPH; DDDD → ACC Description: The program counter (address stack) is pushed down one level. Program control transfers to the next instruction following the last jump to subroutine (JMS) instruction. The 4 bits of data DDDD stored in the OPA portion of the instruction are loaded to the accumulator. BBL is used to return from subroutine main program.
	Mnemonic:   JIN (Jump indirect) OPR OPA: 0011 RRR1 Symbolic: (RRR0) → PM; (RRR1) → PL; PH unchanged Description: The 8 bit content of the designated index register pair is loaded into the low order 8 positions of the program counter. Program control is transferred to the instruction at that address on the same page (same ROM) where the JIN instruction is located. The 8 bit content of the index register is unaffected. Exceptions: When JIN is located at the address (PH) 1111 1111 program control is transferred to the next page in sequence and not to the same page where the JIN instruction is located. That is, the next address is (PH + 1)(RRR0)(RRR1) and not (PH)(RRR0)(RRR1).
	Mnemonic:   SRC (Jump indirect) OPR OPA: 0010 RRR1 Symbolic: (RRR0) → DB (X2); (RRR1) → DB (X3) Description: The 8 bit content of the designated index register pair is sent to the RAM address register at X2 and X3. A subsequent read, write or I/O operation of the RAM will utilize this address. Specifically, the first 2 bits of the address designate a RAM chip; the second 2 bits designate 1 out of 4 registers within the chip; the last 4 bits designate 1 out of 16 4 bit main memory characters within the register. This command is also used to designate a ROM I/O port or an I/O device for a subsequent I/O operation. The address in I/O device, ROM or RAM is not cleared until the next SRC instruction is executed. The 8 bit content of the index register is unaffected.
	Mnemonic:   FIN (Fetch indirect from ROM) OPR OPA: 0011 RRR0 Symbolic: (PH)(0000)(0001) → ROM address; (OPR) → RRR0; (OPA) → RRR1 Description: The 8 bit content of the 0 index register pair (0000) (0001) is sent out as an address in the same page where the FIN instruction is located. The 8 bit word at that location is loaded into the designated index register pair. The program counter is unaffecte; after FIN has been executed the next instruction in sequence will be addressed. The content of the 0 index register pair is unaltered unless index register 0 was designated. Exceptions: a.  Although FIN is a 1-word instruction, its execution requires two instruction cycles. b.  When FIN is located at address (PH) 1111 1111 data will be fetched from the next page (ROM) in sequence and not from the same page (ROM) where the FIN instruction is located. That is, next address is (PH + 1)(0000)(0001) and not (PH)(0000)(0001).
	Mnemonic:   HLT (Executes Halt until interrupt received) OPR OPA: 0000 0001 Symbolic: 1 → HALT; 1 → STOP Description: The processor sets the HALT and STOP flip-flops. Program counter incrementer and data input buffers are inhibited. The processor executes NOP continuously; continuation can occur by means of STOP or INTERRUPT control. In this mode, the Program counter + 1 is gated out at A1, A2 and A3 times on the data bus. M1, M2 times will contain the addressed ROM instruction on the data bus. X1 will contain the 4 bit accumulator contents. X2 and X3 will contain the 8 bit SRC register.
	Mnemonic:   BBS (Return from subroutine and restore SRC) OPR OPA: 0000 0010 Symbolic: (Stack → PL, PM, PH); SRCR0 → DB(X2); SRCR1 → DB(X3) Description: This instruction is a combination of BRANCH BACK and SRC. The effective address counter is decremented and program control is returned to the location saved by the forced JMS which occurred at the beginning of the interrupt routine. In addition, the content of the SRC register is sent out at X2 and X3 of the instruction cycle, thus restoring the I/O port selection. This instruction will also turn off the INTA line reenabling the CPU for Interrupt. The previously selected Index register bank will also be restored during this instruction.
	Mnemonic:   LCR (Data RAM and ROM bank status loaded into accumulator) OPR OPA: 0000 0011 Symbolic: (CR) → ACC Description: The 4 bit contents of the COMMAND REGISTER are transferred to the accumulator. This allows saving the command register values before processing the interrupt.
	Mnemonic:   OR4 (OR accumulator with IR4) OPR OPA: 0000 0100 Symbolic: (RRRR4) | (ACC) → ACC Description: The 4 bit contents of index register #4 are logically "OR-ed" with the accumulator. The result is placed in the accumulator and the carry flip-flop is unaffected. Example: (ACC)  0101 (ACC)  0000 (RRRR4)  1001 (RRRR4)  1000 ACC  1101 ACC  1000
	Mnemonic:   OR5 (OR accumulator with IR5) OPR OPA: 0000 0101 Symbolic: (RRRR5) | (ACC) → ACC Description: The 4 bit contents of index register #5 are logically "OR-ed" with the accumulator. The result is placed in the accumulator and the carry flip-flop is unaffected.
	Mnemonic:   AN6 (AND accumulator with IR6) OPR OPA: 0000 0110 Symbolic: (RRRR6) & (ACC) → ACC Description: The 4 bit contents of index register #6 are logically "AND-ed" with the accumulator. The result is placed in the accumulator and the carry flip-flop is unaffected. Example: (ACC)  0111 (ACC)  1111 (RRRR6)  0100 (RRRR6)  0001 ACC  0100 ACC  0001
	Mnemonic:   AN7 (AND accumulator with IR7) OPR OPA: 0000 0111 Symbolic: (RRRR7) & (ACC) → ACC Description: The 4 bit contents of index register #7 are logically "AND-ed" with the accumulator. The result is placed in the accumulator and the carry flip-flop is unaffected.
	Mnemonic:   DB0 (Select ROM bank 0) OPR OPA: 0000 1000 Symbolic: Enable → CM-ROM0 Description: Designate ROM bank 0. The most significant bit of the command register, CR3, is reset. On the third instruction cycle following its execution, it causes CM-ROM0 to be activated. This bank is selected with reset.
	Mnemonic:   DB1 (Select ROM bank 1) OPR OPA: 0000 1001 Symbolic: Enable → CM-ROM1 Description: Designate ROM bank 1. The most significant bit of the command register, CR3, is set. On the third instruction cycle following its execution, it causes CM-ROM1 to be activated.
	Mnemonic:   SB0 (Select IR bank 0) OPR OPA: 0000 1010 Symbolic: 1 → RB0 Description: Select index register bank 0. The index register bank select flip-flop is reset. Index registers 0 - 7, 8 - 15 will be available for program use. This bank is to be selected with reset.
	Mnemonic:   SB1 (Select IR bank 1) OPR OPA: 0000 1011 Symbolic: 1 → RB1 Description: Select index register bank 1. The index register bank select flip-flop is set. Index registers 0* - 7*, 8 - 15 will be available for program use.
	Mnemonic:   WPM (Write program memory) OPR OPA: 1110 0011 Symbolic: (1111) (SRC) → ROM/RAM address bus (4289); (ACC) → I/O0-I/O3 (4289) Description: Write program memory. When an instruction is to be stored in RAM program memory, it is written in two four-bit segments. The F/L signal from the 4289 keeps track of which half is being written. When the CPU executes a WPM instruction, the chip select lines of the 4289 are jammed with "1111". In the system design this should be designated as the RAM channel. The OUT and PM line on the 4289 are aslo activated by the WPM instruction. The previously selected SRC address on line A0 through A7 of the 4289 becomes the address of the RAM word being written. By appropriately decoding the chip select lines, the W line, and F/L line is initially at logic 0 (VSS) when power comes on and after reset. It then pulses to logic 1 (VDD) when every second WPM is executed. A high on the F/L line means that the first four bits are being written, and a low means that the last four bits are being written. The 4289 transfers the segment of the instruction to the I/O bus at X2 of the WPM instruction. The SRC address sent to RAM is only 8-bits. When more than one page of RAM (256 bytes) is being written, an output port must be used to supply additional address lines for higher order addresses.
	Mnemonic:   RPM (Read program memory) OPR OPA: 0000 1110 Symbolic: (1111) (SRC) → ROM/RAM address bus (4289); (DDDD) → ACC Description: Read program memory.This instruction can be used only with the 4289 standard memory chip. The contents of the previously selected nibble of R/W program memory are transferred to the 4040 and loaded to the accumulator. The F/L 4289 control line is toggled with each RPM. The 4289 IN line and PM line are also active during this instruction.
	Mnemonic:   EIN (Enable interrupt detection) OPR OPA: 0000 1100 Symbolic: 1 → IE Description: Enable interrupt. Internal interrupt detection logic is enabled.
	Mnemonic:   DIN (Disable interrupt detection) OPR OPA: 0000 1101 Symbolic: 0 → IE Description: Disable interrupt. Internal interrupt detection logic is disabled.
D.	Two Word Machine Instructions
	Mnemonic:   JUN (Jump unconditional) 1st word OPR OPA: 0100 A3A3A3A3 2nd word OPR OPA: A2A2A2A2 A1A1A1A1 Symbolic: A1A1A1A1 → PL, A2A2A2A2 → PM, A3A3A3A3 → PH Description: Program control is unconditionally transferred to the instruction locator at the address A3A3A3A3 A2A2A2A2 A1A1A1A1.
	Mnemonic:   JMS (Jump to Subroutine) 1st word OPR OPA: 0101 A3A3A3A3 2nd word OPR OPA: A2A2A2A2 A1A1A1A1 Symbolic: (PHPMPL) → Stack; A1A1A1A1 → PL, A2A2A2A2 → PM, A3A3A3A3 → PH Description: The address of the next instruction in sequence following JMS (return address) is saved in the push down stack. Program control is transferred to the instruction located at the 12 bit address (A3A3A3A3 A2A2A2A2 A1A1A1A1). Execution of a return instruction (BBL) will cause the saved address to be pulled out of the stack, therefore, program control is transferred to the next sequential instruction after the last JMS. The push down stack has 4 registers in 4004, 8 registers in 4040. One of them is used as the program counter, therefore nesting of JMS can occur up to 3 levels in 4004 and 7 levels in 4040. Example (4004):   No JMS received →  Stack         Program counter      →  JPS #1 received →  Stack      Program counter   Return address #1     →    JMS #2 received →  Stack    Program counter   Return address #2   Return address #1     →  JPS #3 received →  Stack  Program counter   Return address #3   Return address #2   Return address #1     →    JMS #4 received →  Stack  Return address #4   Return address #3   Return address #2   Program counter     →  BBL received →  Stack  Program counter   Return address #3   Return address #2
	Mnemonic:   JCN (Jump conditional) 1st word OPR OPA: 0001 C1C2C3C4 2nd word OPR OPA: A2A2A2A2 A1A1A1A1 Symbolic: If C1C2C3C4 is true, A2A2A2A2 → PM, A1A1A1A1 → PL, PH unchanged; If C1C2C3C4 is false, (PH) → PH, (PM) → PM, (PL + 2) → PL Description: If the designated condition code is true, program control is transferred to the instruction located at the 8 bit address 2A2A2A2 A1A1A1A1 on the same page (ROM) where JCN is located. If the condition is not true the next instruction in sequence after JCN is executed. The condition bits are assigned as follows: C1 = 0   Do not invert jump condition C1 = 0   Invert jump condition C2 = 0   Jump if the accumulator content is zero C3 = 0   Jump if the carry/link content is 1 C4 = 0   Jump if test signal (pin 10 on 4004, pin 13 on 4040) is zero CX Condition Table for JCN Instruction C1  C2  C3  C4          0 0 0 0 NO OPERATION 0 0 0 1 Jump if test = 0 (VSS) 0 0 1 0 Jump if CY = 1 0 0 1 1 Jump if test = 0 or CY = 1 0 1 0 0 Jump if AC = 0 0 1 0 1 Jump if test = 0 or AC = 0 0 1 1 0 Jump if CY = 1 or AC = 0 0 1 1 1 Jump if test = 0 or CY = 1 or AC = 0 1 0 0 0 Jump unconditionally 1 0 0 1 Jump if test = 1 (VDD) 1 0 1 0 Jump if CY = 0 1 0 1 1 Jump if test = 1 and CY = 0 1 1 0 0 Jump if AC <> 0 1 1 0 1 Jump if test = 1 and AC <> 0 1 1 1 0 Jump if CY = 0 and AC <> 0 1 1 1 1 Jump if test = 1 and CY = 0 and AC <> 0   NOTE: A logic "1" is the most negative test input. A logic "0" is the most positive test input. Example:   OPR   OPA     0011   0110   Jump if accumulator is zero or carry = 1 Several conditions can be tested simultaneously. The logic equation describing the condition for a jump is given below:   JUMP = C1 . ((ACC = 0) . C2 + (CY = 1) . C3 + TEST . C4) + C1 .  ((ACC = 0) . C2 + (CY = 1) . C3 + TEST. C4) Exceptions:   If JCN is located on words 254 and 255 of a ROM page, when JCN is executed and the condition is true, program control is transferred to the 8-bit address on the page following where JCN is located.
	Mnemonic:   ISZ (Increment index register skip if zero) 1st word OPR OPA: 0111 RRRR 2nd word OPR OPA: A2A2A2A2 A1A1A1A1 Symbolic: (RRRR) + 1 → RRRR, if result = 0 (PH) → PH, (PM) → PM, (PL + 2 →) PL; if result <> 0 A2A2A2A2 → PM, A1A1A1A1 → PL Description: The content of the designated index register is incremented by 1. The accumulator and carry/link are unaffected. If the result is zero, the next instruction after ISZ is executed. If the resultis different from 0, program control is transferred to the instruction located at the 8 bit address A2A2A2A2, A1A1A1A1 on the same page (ROM) where the ISZ instruction is located. Exceptions:   If ISZ is located on words 254 and 255 of a ROM page, when ISZ is executed and the result is not zero, program control is transferred to the 8-bit address on the next page in sequence and not on the same page where ISZ is located.
	Mnemonic:   FIM (Fetched immediate from ROM) 1st word OPR OPA: 0010 RRR0 2nd word OPR OPA: D2D2D2D2 D1D1D1D1 Symbolic: D2D2D2D2 → RRR0; D1D1D1D1 → RRR1 Description: The 2nd word represents 8 bits of data which are loaded into the designated index register pair.
E.	Input/Output Instructions
	The following I/O instructions are described as they relate to ROM and RAM devices. These same instructions (mnemonics) can be redefined for devices other than ROM and RAM.
	Mnemonic:   RDM (Read RAM character) OPR OPA: 1110 1001 Symbolic: (M) → ACC Description: The content of the previously selected RAM main memory character is transferred to the accumulator. The carry/link is unaffected. The 4 bit data in memory is unaffected.
	Mnemonic:   RD0 (Read RAM status character 0) OPR OPA: 1110 1100 Symbolic: (MS0) → ACC Description: The 4 bits of status character 0 from the previously selected RAM register are transferred to the accumulator. The carry/link and the status character are unaffected.
	Mnemonic:   RD1 (Read RAM status character 1) OPR OPA: 1110 1101 Symbolic: (MS1) → ACC Description: The 4 bits of status character 1 from the previously selected RAM register are transferred to the accumulator. The carry/link and the status character are unaffected.
	Mnemonic:   RD2 (Read RAM status character 2) OPR OPA: 1110 1110 Symbolic: (MS2) → ACC Description: The 4 bits of status character 2 from the previously selected RAM register are transferred to the accumulator. The carry/link and the status character are unaffected.
	Mnemonic:   RD3 (Read RAM status character 3) OPR OPA: 1110 1111 Symbolic: (MS3) → ACC Description: The 4 bits of status character 3 from the previously selected RAM register are transferred to the accumulator. The carry/link and the status character are unaffected.
	Mnemonic:   RDR (Read ROM port) OPR OPA: 1110 1010 Symbolic: (ROM input lines) → ACC Description: The data present at the input lines of the previously selected ROM chip is transferred to the accumulator. The carry/link is unaffected. If the I/O option has both inputs and outputs within the same 4 I/O lines, the user can choose to have either "0" or "1" transferred to the accumulator for those I/O pins coded as outputs, when an RDR instruction is executed. Example: Given a port with I/O coded with 2 inputs and 2 outputs, when RDR is executed the transfer is as shown below: I3O2 O1I0 (ACC) 1 X X 0 → 1 (1 or 0) (1 or 0) 0 Input Data User can choose
	Mnemonic:   WRM (Write accumulator into RAM character) OPR OPA: 1110 0000 Symbolic: (ACC) → M Description: The accumulator content is written into the previously selected RAM main memory character location. The accumulator and carry/link are unaffected.
	Mnemonic:   WR0 (Write accumulator into RAM status character 0) OPR OPA: 1110 0100 Symbolic: (ACC) → MS0 Description: The content of the accumulator is written into the RAM status character 0 of the previously selected RAM register. The accumulator and the carry/link are unaffected.
	Mnemonic:   WR1 (Write accumulator into RAM status character 1) OPR OPA: 1110 0101 Symbolic: (ACC) → MS1 Description: The content of the accumulator is written into the RAM status character 1 of the previously selected RAM register. The accumulator and the carry/link are unaffected.
	Mnemonic:   WR2 (Write accumulator into RAM status character 2) OPR OPA: 1110 0110 Symbolic: (ACC) → MS2 Description: The content of the accumulator is written into the RAM status character 2 of the previously selected RAM register. The accumulator and the carry/link are unaffected.
	Mnemonic:   WR3 (Write accumulator into RAM status character 3) OPR OPA: 1110 0111 Symbolic: (ACC) → MS3 Description: The content of the accumulator is written into the RAM status character 3 of the previously selected RAM register. The accumulator and the carry/link are unaffected.
	Mnemonic:   WRR (Write ROM port) OPR OPA: 1110 0010 Symbolic: (ACC) → ROM output lines Description: The content of the accumulator is transferred to the ROM output port of the previously selected ROM chip. The data is available on the output pins until a new WRR is executed on the same chip. The ACC content and carry/link are unaffected. (The LSB bit of the accumulator appears on I/O0.) No operation is performed on I/O lines coded as inputs.
	Mnemonic:   WMP (Write memory port) OPR OPA: 1110 0001 Symbolic: (ACC) → RAM output register Description: The content of the accumulator is transferred to the RAM output port of the previously selected RAM chip. The data is available on the output pins until a new WMP is executed on the same RAM chip. The content of the ACC and carry/link are unaffected. (The LSB bit of the accumulator appears on O0, pin 16 of the 4002.)
	Mnemonic:   ADM (Add from memory with carry) OPR OPA: 1110 1011 Symbolic: (M) + (ACC) + (CY) → ACC, CY Description: The content of the previously selected RAM main memory character is added to the accumulator with carry. The RAM character is unaffected.
	Mnemonic:   SBM (Subtract from memory with borrow) OPR OPA: 1110 1000 Symbolic: (M) + (ACC) + (CY) → ACC, CY Description: The content of the previously selected RAM main memory character is subtracted from the accumulator with borrow. The RAM character is unaffected.
F.	Accumulator Group Instructions
	Mnemonic:   CLB (Clear both) OPR OPA: 1111 0000 Symbolic: 0 → ACC, 0 → CY Description: Set accumulator and carry/link to 0.
	Mnemonic:   CLC (Clear carry) OPR OPA: 1111 0001 Symbolic: 0 → CY Description: Set carry/link to 0.
	Mnemonic:   CMC (Complement carry) OPR OPA: 1111 0011 Symbolic: (CY) → CY Description: The carry/link content is complemented.
	Mnemonic:   STC (Set carry) OPR OPA: 1111 1010 Symbolic: 1 → CY Description: Set carry/link to a 1.
	Mnemonic:   CMA (Complement accumulator) OPR OPA: 1111 0100 Symbolic: (ACC) → CY Description: The content of the accumulator is complemented. The carry/link is unaffected.
	Mnemonic:   IAC (Increment accumulator) OPR OPA: 1111 0010 Symbolic: (ACC) + 1 → ACC Description: The content of the accumulator is incremented by 1. No overflow sets the carry/link to 0, overflow sets the carry/link to a 1.
	Mnemonic:   DAC (Decrement accumulator) OPR OPA: 1111 1000 Symbolic: (ACC) - 1 → ACC Description: The content of the accumulator is incremented by 1. A borrow sets the carry/link to 0, no borrow sets the carry/link to a 1. Example:   a3a2a1a0  ← (ACC) + 1 1 1 1    carry →  c4 s3s2s1s0  ← ACC
	Mnemonic:   RAL (Rotate left) OPR OPA: 1111 0101 Symbolic: CY → a0, ai → ai+1, a3 → CY Description: The content of the accumulator and carry/link are rotated left.
	Mnemonic:   RAR (Rotate right) OPR OPA: 1111 0110 Symbolic: a0 → CY, ai → ai-1, CY → a3 Description: The content of the accumulator and carry/link are rotated right.
	Mnemonic:   TCC (Transmit carry and clear) OPR OPA: 1111 0111 Symbolic: 0 → ACC, (CY) → a0, 0 → CY Description: The accumulator is cleared. The least significant position of the accumulator is set to the value of the carry/link. The carry/link is set to 0.
	Mnemonic:   DAA (Decimal adjust accumulator) OPR OPA: 1111 1011 Symbolic: ACC + 0000 → ACC or ACC + 0110 → ACC Description: The accumulator is incremented by 6 if either the carry/link is 1 or if the accumulator content is greater than 9. The carry/link is set to 1 if the result generates a carry, otherwise is unaffected.
	Mnemonic:   TCS (Transmit carry subtract) OPR OPA: 1111 1001 Symbolic: 1001 → ACC if (CY) = 0, 1010 → ACC if (CY) = 1; 0 → CY Description: The accumulator is set to 9 if the carry/link is 0. The accumulator is set to 10 if the carry/link is a 1. The carry/link is set to 0.
	Mnemonic:   KBP (Keyboard process) OPR OPA: 1111 1100 Symbolic: (ACC) → KBP, ROM → ACC Description: A code conversion is performed on the accumulator content, from 1 out of n to binary code. If the accumulator content has more than one bit on, the accumulator will be set to 15 (to indicate error). The carry/link is unaffected. The conversion table is shown below. (ACC) before KBP (ACC) after KBP 0 0 0 0   →   0 0 0 0 0 0 0 1   →   0 0 0 1 0 0 1 0   →   0 0 1 0 0 1 0 0   →   0 0 1 1 1 0 0 0   →   0 1 0 0 0 0 1 1   →   1 1 1 1 0 1 0 1   →   1 1 1 1 0 1 1 0   →   1 1 1 1 0 1 1 1   →   1 1 1 1 1 0 0 1   →   1 1 1 1 1 0 1 0   →   1 1 1 1 1 0 1 1   →   1 1 1 1 1 1 0 0   →   1 1 1 1 1 1 0 1   →   1 1 1 1 1 1 1 0   →   1 1 1 1 1 1 1 1   →   1 1 1 1
	Mnemonic:   DCL (Designate command line) OPR OPA: 1111 1101 Symbolic: a0 → CM0, a1 → CM1, a2 → CM2 Description: The content of the three least significant accumulator bits is transferred to the command control register within the CPU. This instruction provides RAM bank selection when multiple RAM banks are used. (If no DCL instruction is sent out, RAM bank number zero is automatically selected after application of at least one RESET). DCL remains latched until it is changed. The selection is made according to the following truth table. (ACC)   CM-RAMi Enabled   Bank No. X 0 0 0   CM-RAM0   Bank 0 X 0 0 1   CM-RAM1   Bank 1 X 0 1 0   CM-RAM2   Bank 2 X 1 0 0   CM-RAM3   Bank 3 X 0 1 1   CM-RAM1, CM-RAM2   Bank 4 X 1 0 1   CM-RAM1, CM-RAM3   Bank 5 X 1 1 0   CM-RAM2, CM-RAM3   Bank 6 X 1 1 1   CM-RAM1, CM-RAM2, CM-RAM3   Bank 7

4040 PROGRAMMING TECHNIQUES
Use of Designate ROM Bank Instructions

The DB instructions present a convenient method of switching from one ROM bank to another. As shown in the following examples, the bank switch is delayed until the 3rd instruction cycle after the DB is executed.

Example #1:
ROM Location*						Instruction		Comment
Bank	/	Page	/	Word
0		2		107		X X X
0		2		108		DB1		Designate Bank 1.
0		2		109		JUN 1
0		2		110		27		During this instruction cycle a "1" is loaded in bit #3 of the command register.
1		1		27		X X X		JUN occured to Bank 1 because CM-ROM1 has been activated.
.						.
.						.
.						.
1		1		63		DB0		Designate Bank 0.
1		1		64		ISZ 3
1		1		65		151
0		1		66		X X X		Program jumps here if (IR3) = 0.
0		1		151		X X X		Program jumps here if (IR3) <> 0.
Example #2:
ROM Location*						Instruction		Comment
Bank	/	Page	/	Word
0		7		131		X X X
0		7		132		DB1		Designate Bank 1.
0		7		133		JMS 2
0		7		134		96		Address 7, 135 saved in stack.
1		2		96		X X X		JMS occurs to 1, 2, 96 since CM-ROM1 is activated at that instruction cycle.
.						.
.						.
.						.
1		2		170		DB0		Designate Bank 0.
1		2		171		XCH 7
1		2		172		BBL		Address 7, 135 pulled from stack and placed in PC; branch back occurs to 7, 135 in Bank 0 because CM-ROM0 is activated during this instruction cycle.
0		7		135		X X X		Program jumps here if (IR3) = 0.
* Bank #0, 1     Page #0 - 15     Word #0 - 255

	CYCLE #1								CYCLE #2								CYCLE #3								CYCLE #4								CYCLE #5
	A1	A2	A3	M1	M2	X1	X2	X3	A1	A2	A3	M1	M2	X1	X2	X3	A1	A2	A3	M1	M2	X1	X2	X3	A1	A2	A3	M1	M2	X1	X2	X3	A1	A2	A3	M1	M2	X1	X2	X3
SYNC	1	1	1	1	1	1	1	0	1	1	1	1	1	1	1	0	1	1	1	1	1	1	1	0	1	1	1	1	1	1	1	0	1	1	1	1	1	1	1	0
DECODED DB1	1	1	1	1	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ROM BANK FLIP-FLOP	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
CM ROM0	1	1	0	0	1	1	1	1	1	1	0	0	1	1	1	1	1	1	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
CM ROM1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0*	1	1	1	1	1	1	0	0*	1	1	1	1
	DBI INSTRUCTION								2 CYCLE DELAY ALLOWS JUMP INSTRUCTION																DBI TAKES EFFECT
	BANK 0																								BANK 1
*If first instruction cycle of instruction execution for 4040, CM remains low (VDD) until M2.

Interrupt Processing

   The Interrupt signal, when aremd and activated, causes the CPU to suspend normal program execution. The CPU is forced to execute a predermined interrupt subroutine starting from location 003. At the completion of the interrupt routine, the CPU is returned to the normal program execution with a BBS instruction.
   The interrupt utilizes the address push down stack. When an interrupt is executed, the program counter is pushed up one level and is reloaded with address 003. Execution will proceed from this location. The location may contain jump (JIN, JUN) which allows the user to place the interrupt routine anywhere in memory. A stack level should always be reserved for the interrupts to avoid overflowing the stack.
   Since the interrupt forces the CPU out of the normal instruction sequence, the state of the CPU's internal register values must be preserved and restored prior to returning from the interrupt routine. The SRC and the index register bank will automatically be saved. The designer should store the value of the accumulator and carry flip-flop, command register, current ROM bank, and index registers that will be used during the interrupt execution.
   The 4040 CPU has three groups of eight index registers organized into two banks. Registers 8-15 are common to both. Bank 0, register 0-7 can be designated for normal program execution while Bank 1, register 0^*-7^* can be designated for interrupt execution. The designer needs only switch banks to save the first eight register values. These will be restored automatically with the BBS.
   The programmer must first enable the CPU to accept an interrupt. This is done by executing the EIN instruction. When an interrupt occurs, the program counter is forced to location 003 in whichever ROM bank it is executing.
   An interrupt processing routine is, in general, composed of three distinct parts:
      a. The instructions required to save the current processor status.
      b. A portion which determines and services the interrupting device.
      c. The instructions required to restore program control to the pre-interrupt conditions.    In the following example, the processor issued with a single ROM bank, and index register (IR) bank 1 is used to save status (accumulator/carry, command register (CR)). The six remaining registers in IR bank 1 are available for interrupt servicing. In addition to being relatively simple, this scheme has the advantage of saving processor status with the fewest number of instructions. Note that since only one ROM bank is available, it is only necessary to save the lower three bits of CR. This allows saving the CR and CY to be merged in the same register location.

Example #3:
ROM Location*						Instruction		Comment
Bank	/	Page	/	Word
0		6		82		SRC 4		(IR 8, 9) sent to ROM & RAM, Load SRC Reg.
0		6		83		INC 9		Interrupt occurs here.
0		6		84		(JMS 0)		Interrupt acknowledged, 6, 84 saved in stack; instruction at 6, 84 ignored.
0		6		84		(3)
0		0		3		SB1		Select IR Bank 1.
0		0		4		XCH 7		(ACC) → IR7 - ACC saved.
0		0		5		LCR		(CR) → ACC
0		0		6		RAL		(CY) → ACC0, ACC0 → ACC1 ... ACC3 → CY
0		0		7		XCH 6		(ACC) → IR6 CY, CR saved.
0		0		8
0		0		9		.		Routine for determining and servicing interrupt is executed here.
.						.
.						.
.						.
0		P		n		XCH 6		(IR6) → ACC
				n+1		RAR		ACC0 → CY - CY restored
				n+2		DCL		ACC0 → CR0, ACC1 → CR1, ACC2 → CR2, CR restored
				n+3		XCH 7		(IR7) → ACC
				n+4		BBS		Address 6, 84 loaded into PC; contents of SRC register sent out and the index register bank selection is restored. The interrupt acknowledge line is cleared to VSS.
0		6		84		WRM		Program restored*.
* Index Register Bank is automatically restored with BBS