6502 instruction set

  x0  x1  x2  x3  x4  x5  x6  x7  x8  x9  xA  xB  xC  xD  xE  xF 
 0x BRK
2 7
---I--		ORA (a8,X)
2 6
NZ----		   ORA a8
2 3
NZ----		ASL a8
2 5
NZC---		 PHP
1 3
------		ORA #d8
2 2
NZ----		ASL A
1 2
NZC---		  ORA a16
3 4
NZ----		ASL a16
3 6
NZC---		 
 1x BPL r8
2 3+/2
------		ORA (a8),Y
2 5+
NZ----		   ORA a8,X
2 4
NZ----		ASL a8,X
2 6
NZC---		 CLC
1 2
--C---		ORA a16,Y
3 4+
NZ----		   ORA a16,X
3 4+
NZ----		ASL a16,X
3 7
NZC---		 
 2x JSR a16
3 6
------		AND (a8,X)
2 6
NZ----		  BIT a8
2 3
NZ---V		AND a8
2 3
NZ----		ROL a8
2 5
NZC---		 PLP
1 4
NZCIDV		AND #d8
2 2
NZ----		ROL A
1 2
NZC---		  BIT a16
3 4
NZ---V		AND a16
3 4
NZ----		ROL a16
3 6
NZC---		 
 3x BMI r8
2 3+/2
------		AND (a8),Y
2 5+
NZ----		   AND a8,X
2 4
NZ----		ROL a8,X
2 6
NZC---		 SEC
1 2
--C---		AND a16,Y
3 4+
NZ----		   AND a16,X
3 4+
NZ----		ROL a16,X
3 7
NZC---		 
 4x RTI
1 6
NZCIDV		EOR (a8,X)
2 6
NZ----		   EOR a8
2 3
NZ----		LSR a8
2 5
NZC---		 PHA
1 3
------		EOR #d8
2 2
NZ----		LSR A
1 2
NZC---		 JMP a16
3 3
------		EOR a16
3 4
NZ----		LSR a16
3 6
NZC---		 
 5x BVC r8
2 3+/2
------		EOR (a8),Y
2 5+
NZ----		   EOR a8,X
2 4
NZ----		LSR a8,X
2 6
NZC---		 CLI
1 2
---I--		EOR a16,Y
3 4+
NZ----		   EOR a16,X
3 4+
NZ----		LSR a16,X
3 7
NZC---		 
 6x RTS
1 6
------		ADC (a8,X)
2 6
NZC--V		   ADC a8
2 3
NZC--V		ROR a8
2 5
NZC---		 PLA
1 4
NZ----		ADC #d8
2 2
NZC--V		ROR A
1 2
NZC---		 JMP (a16)
3 5
------		ADC a16
3 4
NZC--V		ROR a16
3 6
NZC---		 
 7x BVS r8
2 3+/2
------		ADC (a8),Y
2 5+
NZC--V		   ADC a8,X
2 4
NZC--V		ROR a8,X
2 6
NZC---		 SEI
1 2
---I--		ADC a16,Y
3 4+
NZC--V		   ADC a16,X
3 4+
NZC--V		ROR a16,X
3 7
NZC---		 
 8x  STA (a8,X)
2 6
------		  STY a8
2 3
------		STA a8
2 3
------		STX a8
2 3
------		 DEY
1 2
NZ----		 TXA
1 2
NZ----		 STY a16
3 4
------		STA a16
3 4
------		STX a16
3 4
------		 
 9x BCC r8
2 3+/2
------		STA (a8),Y
2 6
------		  STY a8,X
2 4
------		STA a8,X
2 4
------		STX a8,Y
2 4
------		 TYA
1 2
NZ----		STA a16,Y
3 5
------		TXS
1 2
------		  STA a16,X
3 5
------		  
 Ax LDY #d8
2 2
NZ----		LDA (a8,X)
2 6
NZ----		LDX #d8
2 2
NZ----		 LDY a8
2 3
NZ----		LDA a8
2 3
NZ----		LDX a8
2 3
NZ----		 TAY
1 2
NZ----		LDA #d8
2 2
NZ----		TAX
1 2
NZ----		 LDY a16
3 4
NZ----		LDA a16
3 4
NZ----		LDX a16
3 4
NZ----		 
 Bx BCS r8
2 3+/2
------		LDA (a8),Y
2 5+
NZ----		  LDY a8,X
2 4
NZ----		LDA a8,X
2 4
NZ----		LDX a8,Y
2 4
NZ----		 CLV
1 2
-----V		LDA a16,Y
3 4+
NZ----		TSX
1 2
NZ----		 LDY a16,X
3 4+
NZ----		LDA a16,X
3 4+
NZ----		LDX a16,Y
3 4+
NZ----		 
 Cx CPY #d8
2 2
NZC---		CMP (a8,X)
2 6
NZC---		  CPY a8
2 3
NZC---		CMP a8
2 3
NZC---		DEC a8
2 5
NZ----		 INY
1 2
NZ----		CMP #d8
2 2
NZC---		DEX
1 2
NZ----		 CPY a16
3 4
NZC---		CMP a16
3 4
NZC---		DEC a16
3 6
NZ----		 
 Dx BNE r8
2 3+/2
------		CMP (a8),Y
2 5+
NZC---		   CMP a8,X
2 4
NZC---		DEC a8,X
2 6
NZ----		 CLD
1 2
----D-		CMP a16,Y
3 4+
NZC---		   CMP a16,X
3 4+
NZC---		DEC a16,X
3 7
NZ----		 
 Ex CPX #d8
2 2
NZC---		SBC (a8,X)
2 6
NZC--V		  CPX a8
2 3
NZC---		SBC a8
2 3
NZC--V		INC a8
2 5
NZ----		 INX
1 2
NZ----		SBC #d8
2 2
NZC--V		NOP
1 2
------		 CPX a16
3 4
NZC---		SBC a16
3 4
NZC--V		INC a16
3 6
NZ----		 
 Fx BEQ r8
2 3+/2
------		SBC (a8),Y
2 5+
NZC--V		   SBC a8,X
2 4
NZC--V		INC a8,X
2 6
NZ----		 SED
1 2
----D-		SBC a16,Y
3 4+
NZC--V		   SBC a16,X
3 4+
NZC--V		INC a16,X
3 7
NZ----		 


       Misc/control instructions
       Jumps/branches/calls
       Load/store/transfer instructions
       Arithmetic/logical instructions
       Shift/rotation instructions
  
 
Length in bytes →
 		   INS a8
2 3
NZCIDV		   ← Instruction mnemonic
← Duration in cycles
← Flags affected
  Duration of conditional branches is 2 cycles when branch is not taken, 3 cycles when branch is taken and 4 cycles when branch is taken and crosses 256 byte page boundary. This is indicated with +.
Duration of instructions with indexed addressing is in some cases one cycle longer, when while calculating target address 256 byte page boundary is crossed. This is indicated with + after digit.