Intel 8085 Partial Schematic

Intel 8085 partial schematic

1. Basic signals

PHI1 and PHI2

Schematic with FETs.

RESET

Schematic with FETs.

Figure 1 - PHI1, PHI2 and RESET signals

Note the yellow strips (PHI1 active) and cyan strips (PHI2 active).
X1 and X2 pads are connected to the Pierce oscillator. It contains inverting Schmitt trigger. The signal from the oscillator is divided by 2 and then goes thru flip-flop which makes the non overlapping clock signals PHI1 and PHI2 which synchronize everything in the chip. PHI1 is then negated and amplified and goes out to the pad CLK (OUT). So CLK (OUT) is in phase with PHI2 but has different duty cycle.
Changes in /RESET IN signal are recognized during PHI2 phase. The signal is conditioned by inverting Schmitt trigger. It is postponed until next PHI1 phase and routed as signal RESET throughall the chip. Then it is postponed to the next PHI2 phase (so it is in phase with CLK (OUT)), amplified and goes out to the pad RESET OUT.

2. Instruction register and decode ROM

Instruction register

Schematic with FETs.

Figure 2 - INS_B* signals going from instruction register

Only three lowest bits are shown here. The rest of the register is analogous. The output signals not shown here are INS_B3, /INS_B3 ... INS_B7 and /INS_B7. Additional 9 signals (first 3 shown) are created via PHI2. Those signals are /INS_B0@2, INS_B1@2, INS_B2@2, INS_B3@2, /INS_B3@2, INS_B4@2, /INS_B4@2, INS_B5@2 and /INS_B5@2.
The instruction register is loaded from data bus. Loading is triggered by signal INS_LOAD which is high when CYC_M1, T3 and PHI1 signals are high. Or - when RESET and PHI1 is high.
Many parts of the chip are controlled by basic timing signals for cycle identification (CYC_M1, CYC_R1, CYC_R2, CYC_W1 and CYC_W2) and for state identification (T1, T2, T3, T4, T5 and T6). All those cycles are one phase ahead of real machine cycles and states so that the logic has time to settle down before any action is triggered.

Following table explains it better (HLD_CYC and NXT_INS signals will be explained later):

Table 1

TIME					SIGNALS									ACTION
clock	instruction	cycle	state	phase	CYC_M1	CYC_R1	CYC_R2	T1	T2	T3	T4	HLD_CYC	NXT_INS	ACTION
1	MVI A,xx	M1	T1	PHI1	1	0	0	1	0	0	0	1	0
1	MVI A,xx	M1	T1	PHI2	1	0	0	0	1	0	0	1	0
2	MVI A,xx	M1	T2	PHI1	1	0	0	0	1	0	0	1	0	opcode fetch
2	MVI A,xx	M1	T2	PHI2	1	0	0	0	0	1	0	1	0	opcode fetch
3	MVI A,xx	M1	T3	PHI1	1	0	0	0	0	1	0	1	0	opcode fetch
3	MVI A,xx	M1	T3	PHI2	1	0	0	0	0	0	1	1	0
4	MVI A,xx	M1	T4	PHI1	1	0	0	0	0	0	1	0	0
4	MVI A,xx	M1	T4	PHI2	0	1	0	1	0	0	0	0	0
5	MVI A,xx	R1	T1	PHI1	0	1	0	1	0	0	0	1	0
5	MVI A,xx	R1	T1	PHI2	0	1	0	0	1	0	0	1	0
6	MVI A,xx	R1	T2	PHI1	0	1	0	0	1	0	0	1	0	memory read
6	MVI A,xx	R1	T2	PHI2	0	1	0	0	0	1	0	1	0	memory read
7	MVI A,xx	R1	T3	PHI1	0	1	0	0	0	1	0	0	1	memory read
7	MVI A,xx	R1	T3	PHI2	1	0	0	1	0	0	0	0	1
8	LXI H,xxyy	M1	T1	PHI1	1	0	0	1	0	0	0	1	0
8	LXI H,xxyy	M1	T1	PHI2	1	0	0	0	1	0	0	1	0
9	LXI H,xxyy	M1	T2	PHI1	1	0	0	0	1	0	0	1	0	opcode fetch
9	LXI H,xxyy	M1	T2	PHI2	1	0	0	0	0	1	0	1	0	opcode fetch
10	LXI H,xxyy	M1	T3	PHI1	1	0	0	0	0	1	0	1	0	opcode fetch
10	LXI H,xxyy	M1	T3	PHI2	1	0	0	0	0	0	1	1	0
11	LXI H,xxyy	M1	T4	PHI1	1	0	0	0	0	0	1	0	0
11	LXI H,xxyy	M1	T4	PHI2	0	1	0	1	0	0	0	0	0
12	LXI H,xxyy	R1	T1	PHI1	0	1	0	1	0	0	0	1	0
12	LXI H,xxyy	R1	T1	PHI2	0	1	0	0	1	0	0	1	0
13	LXI H,xxyy	R1	T2	PHI1	0	1	0	0	1	0	0	1	0	memory read
13	LXI H,xxyy	R1	T2	PHI2	0	1	0	0	0	1	0	1	0	memory read
14	LXI H,xxyy	R1	T3	PHI1	0	1	0	0	0	1	0	0	0	memory read
14	LXI H,xxyy	R1	T3	PHI2	0	0	1	1	0	0	0	0	0
15	LXI H,xxyy	R2	T1	PHI1	0	0	1	1	0	0	0	1	0
15	LXI H,xxyy	R2	T1	PHI2	0	0	1	0	1	0	0	1	0
16	LXI H,xxyy	R2	T2	PHI1	0	0	1	0	1	0	0	1	0	memory read
16	LXI H,xxyy	R2	T2	PHI2	0	0	1	0	0	1	0	1	0	memory read
17	LXI H,xxyy	R2	T3	PHI1	0	0	1	0	0	1	0	0	1	memory read
17	LXI H,xxyy	R2	T3	PHI2	1	0	0	1	0	0	0	0	1

All logical values were sampled at the falling edge of corresponding PHI1 or PHI2 signal.
So as we have seen above - the instruction register is loaded from the data bus when signals CYC_M1, T3 and PHI1 are high. From the table above it is clear that this happens in cycle M1, state T3 and phase PHI1, exactly when opcode fetch ends.
Additional signals passed thru PHI2 are delayed by some halfphase and thus their changes are aligned with T3 - see figure 2 where transition from instruction 3E (MVI A,xx) to instruction 21 (LXI H,xxyy) is shown.

INS_M1 and INS_M2

Schematic with FETs.

Those two signals are used in instruction decode ROM to distinguish instructions with register argument (A, B, C, D, E, H, L) and memory argument (M pseudoregister).

Instruction decode ROM

Schematic with FETs.

In the schematic above is only a part of the ROM. The listing of the whole ROM is here. Read it now before you continue. The order of the signals is the same as in the real chip.
All 18 input signals are decoded in 48 groups of instructions. If there is need to distinguish a particular instruction within the group it is done in logic elsewhere. There is no signal for NOP instruction as it doesn't require any particular action.
All 48 signals are routed to the instruction timing ROM where is the most of the informations for creating timing signals like CYC_M1 or T1.
Only 46 signals are routed to other decoding ROMs where signals for ALU or register file are created. The exception is INS_DI_EI and INS_HLT because those instructions don't need registers or ALU.

3. Instruction timing ROM and cycle signals

Instruction timing ROM

Figure 3 - basic cycle (CYC_M1, CYC_R1) and state (T1, T2, T3, T4) signals

As it can be seen from the Figure 3 and Table 1 all timing signals are one phase ahead. Cycle (CYC_M1, CYC_R1, etc.) and state (T1, T2, etc.) are changing their value at the beginning of PHI2.
There are two other signals which controll the instruction cycle timing. One is HLD_CYC which tells the timing logic that current cycle signal should be held. When this signal goes down (at the beginning of PHI1) the current cycle is finished and the next one in order starts at the beginning of the next PHI2 phase.
The other signal is NXT_INS. It goes up in the same time when HLD_CYC goes down at the end of the instruction. So it tells the timing logic that all the cycles for the current instruction are done and the next cycle is CYC_M1 of the next instruction.
Note that when there are two consecutive one-cycle instructions like two NOPs the HLD_CYC normally goes down and NXT_INS goes up between them, but the CYC_M1 doesn't change and is up without interruption as expected.

/CYC_M1 signal

Schematic with FETs.

This signal goes up when HLD_CYC goes down (i.e. previous cycle should end) and NXT_INS goes up (i.e. next instruction starts, of course with M1 cycle). This happens at the beginning of PHI1. This condition propagates thru PHI2 at the output of this circuit.
The HLD_CYC and NXT_INS must stay intact during PHI2 so that their eventual change is not propagated to the output. NXT_INS and HLD_CYC change back at the PHI1 so possible race condition in input AND-OR-INVERT is not propagated at the output as its result is scanned during PHI2.
And this cycle signal is held until HLD_CYC goes down and NXT_INS doesn't go up.

/CYC_R1 signal

Schematic with FETs.

This signal goes up when HLD_CYC is low (i.e. previous cycle - here M1 - should end) and NXT_INS is low i.e. current isntruction continues and /CYC_M1 is low i.e. previsous cycle was M1 and both /INS_SKP_Rx and /INS_SKP_R1 should be inactive (i.e. in 1).
/CYC_M1 is passed via PHI1 because it must not change during the next PHI2 phase.
Cycle R1 is skipped when /INS_SKP_R1 or /INS_SKP_Rx are active (i.e. in 0).
R1 cycle ends when HLD_CYC goes down.

/CYC_R2 signal

Schematic with FETs.

This signal goes up when HLD_CYC is low (i.e. previous cycle - here R1 or M1 - should end) and NXT_INS is low i.e. current isntruction continues and /CYC_R1 is down i.e. previous cycle was R1 or both /CYC_M1 and /INS_SKP_R1 are down i.e. previous cycle was M1 and /INS_SKP_R1 is active (i.e. in 0).
Both /CYC_M1 and /CYC_R1 are passed via PHI1 because it must not change during the next PHI2 phase.
Both R1 and R2 cycles are skipped when /INS_SKP_Rx is active. Note that /INS_SKP_R1 and /INS_SKP_Rx are never active (i.e. 0) at the same time.
R2 cycle ends when HLD_CYC goes down.

/CYC_W1 signal

Schematic with FETs.

This signal goes up when HLD_CYC is low (i.e. previous cycle - here R2 or M1 - should end) and NXT_INS is low i.e. current isntruction continues and /CYC_R2 is down i.e. previous cycle was R2 or both /CYC_M1 and /INS_SKP_Rx are down i.e. previous cycle was M1 and /INS_SKP_Rx is active (i.e. in 0).
Both /CYC_M1 and /CYC_R2 are passed via PHI1 because it must not change during the next PHI2 phase.
W1 cycle ends when HLD_CYC goes down.

/CYC_W2 signal

Schematic with FETs.

This signal goes up when HLD_CYC is low (i.e. previous cycle - here W1 - should end) and NXT_INS is low i.e. current isntruction continues and /CYC_RW is down i.e. previous cycle was W1.
/CYC_W1 is passed via PHI1 because it must not change during the next PHI2 phase.
W2 cycle ends when HLD_CYC goes down.

HLD_CYC signal

Schematic with FETs.

This one is pretty easy. It goes down when other cycle than M1 is active and T3 state is on. Or when T6 is on - this happens only while CYC_M1 is active or when T4 is on and /INS_LNG is inactive (i.e. 1).
The result is passed via PHI1 which delays it by one phase exactly as it is needed in all CYC_x circuits above.
/INS_LNG signal causes M1 cycle to be 6 states long when active (i.e. 0).
/M1_END signal is used in NXT_INS circuit which is more complicated. We have to look at the flag logic before.
RESET signal finishes current cycle immediately i.e. current T state is the last.

FLAG_MET signal

Schematic with FETs.

First let's look at the TEST_FLAG signal. It is high one state after T4 at PHI1. During every instruction. For Rcc and RSTV instructions that means cycle M1, state T5, phase PHI1 (CYC_M1, T5 and PHI1 are high).
For Jcc, Ccc, JNK and JK instructions it means cycle R1, state T1, phase PHI1 (CYC_R1, T1 and PHI1 are high).
Testing of the flags consists of three differenct sources. All sources are combinations of INS_B*@2 signals and of DB_* passed by PHI2. This means that the result of the flag test is stabilized during the next PHI1 phase when TEST_FLAG is high.
First source is /ccFLAG_MET which is low when NZ, Z, NC, C, PO, PE, P, M conditions are met. The second source is /KFLAG_MET which tests NK and K conditions. The last source tests V flag.
The result is put into register and held there until the next test which takes place in the next instruction.

Jcc_Ccc_NOT_TKN and Rcc_RSTV_NOT_TKN signals

Schematic with FETs.

Here the /FLAG_MET (i.e. condition is false) is combined with two groups of conditional instructions. The result is Rcc_RSTV_NOT_TKN i.e. Rcc or RSTV instructions don't take place and are interrupted.
The same logic works for Jcc_Ccc_NOT_TKN signal - i.e. condition is false and jump or call shouldn't take place.

NXT_INS signal

Schematic with FETs.

NXT_INS tells the timing logic that current instruction is about to end. It could be forced by RESET signal (the same case as with HLD_CYC signal). During the reset all T* states signals are switched off and CYC_M1 is switched on.
All conditional instructions are tested here. So if Rcc and RSTV instructions shouldn't be fully executed the while T6 signal is on the NXT_INS signal tells the timing logic that those instructions should be prematurely finished and next instruction should be executed.
The same is true for Jcc, Ccc and JNK, JK instructions when T3 and CYC_R1 signals are on. Another condition tells that when M1 cycle ends (told by /M1_END signal) and all /INS_E* are inactive (i.e. 1) no other cycle should be performed and M1 should be the only cycle of the instruction.
The rest of the logic desides which cycle should be the last (while T3 signal is high) - see following table:

Table 2

/INS_E1	/INS_E2	/INS_E3	last cycle
1	1	1	M1
1	1	0	W1
1	0	1	R2
1	0	0	R1
0	1	1	W2

The output is passed via PHI1 to occur exatly at the same time as HLD_CYC as the CYC_* circuits require.

4. State signals and related logic

HOLD and HLDA pads and logic

Schematic with FETs.

Figure 4 - HOLD state and HOLD signal

Before we look at the T1 to T6 signals we have to understand several othe parts of the CPU.
HOLD signal is scanned during PHI2. The result is held in flip flop. Note that 3-input NOR in that flip flop has additional pull-up to, probably to improve its rising edge. See schematic with FETs - additional pull-up gives more charge during PHI1 while the state of the whole flip flop can be changed during PHI2.
The output from this flip flop (HOLD_FF) is propagated further via another pass transistor controlled by LD_HLD signal. It's active during PHI1 of T3 or T5 or when HLT_HLD signal is active or when the HLD signal is active.
This means - when the HOLD signal is activated, it's change is registered during PHI2. When no HLT_HLD is on (i.e. CPU is halted after HLT instruction) this signal is propagated further during the PHI1 of T3 or T5.
This means all read/write operations of the current cycle are successfully done and the CPU can put the buses into high impedancy state and internally finish the current cycle if necessary. CPU starts another cycle but doesn't start T1 state so it effectively stops.
So the signal is propagated and stored in another flip flop. The signal HLD is created and amplified and used elsewhere in the chip. The result is passed via PHI2 and thus postponed to the PHI2 phase of the state T3 or T5. It is amplified and put out to the HLDA pad.
This tells that in the next state the chip's buses will be put into third state. And indeed, we can see that HLD signal is passed via PHI2 (so PHI2 phase of T3 or T5) and then via PHI1 (so PHI1 phase of state T4 or T6 or "next cycle's T1" - which in fact don't occur because CPU is halted) and HADR_EN and /HADR_EN signals are created.
So once more - when HOLD occurres in M1 cycle all remaining states are finished and the next cycle's T1 state is not started, while when it occures in any other cycle there are no other states to finish as the T3 is the last state so only no other cycle's T1 is started.
HADR_EN means "high address enable" so when it is low the A8-A15, IO/_M, /RD and /WR are put into high impedancy state. Note that high impedancy for AD0-AD7 is solved elsewhere by LADR_EN signal.
Where CPU is halted after HLT instruction (HLT_HLD signal is high) no T3 or T5 can occur but result from the first flip flop is put at the next PHI1 instead. Note also that HLT_HLD signal is high also when RESET signal is high which can interrupt a HOLD state prematurely.
There is also a feed back of the HLD signal to the 4-input OR so that when HOLD input goes back down the logic is not waiting for the T3 or T5 state as they don't occur and the signal is propagated in the next PHI1 phase instead.
Signal HADR_EN is influenced by HLT_HLD as well.

HLT_HLD signal

Schematic with FETs.

Figure 5 - HLT instruction - going into HALT state

In the figure 5 we can see what happens after HLT instruction. First - decoded signal INS_HLT goes up during PHI1 of T3 as expected. As we can see 3 conditions must be fulfilled so that CPU gets halted.
First one is that INS_HLT must be high.
The second one is T1@1 (which is T1 signal delayed by one phase i.e. passed via PHI1) must be high. Note that as T1 signal is one phase ahead T1@1 is high when CPU is in T1 state. Or CPU must already be halted. This means halt state is triggered by INS_HLT and T1@1 and then it is held.
The third condition is that /INS_INT must be high i.e. there is no interrupt (all kinds INTR, TRAP, and RST*.5) being performed. When interrupt is just to be performed the CPU does not goe into HALT state and HLT instruction takes normally four T states as expected.
Or when CPU went to HOLD state during HLT instruction it can prevent interrupt to be performed and CPU normally goes into HALT state. It is both in HOLD and HALT state at the same time. Which is quite normal - while being in HALT state the CPU can anytime go from/into HOLD state.
/HLT_HLD@-2 signal is created immediately. That @-2 at the end of signal's name means that it has to be passed via PHI2 to become HLT_HLD. Well not very clever, but I decided to name it so...
After one phase HLT_HLD signal is created and after another one HLT_HLD@1 is created and HADR_EN goes down which tri-states the buses.
Note that there is another extra condition - when RESET is high HLT_HLD signal goes high as well.
Note that there is a possible race condition as T1@1 goes down at the same time as /HLT_HLD@-2 goes up. But the chip works well.

T1 signal

Schematic with FETs.

Figure 6 - HLT instruction interrupted by INTR signal

Here the T1 signal is created. Here it is clear that HLD or RESET can prevent the creation of T1 - CPU is stopped in that case. We can see as well that there are 3 ways how the T1 pulse can be created.
The first and most common - it is created from /HLD_CYC signal which denotes the end of the previous cycle.
The second way is used when CPU goes out of HALT state. T1 is created when both HLT_HLD@1 and /HLT_HLD@-2 are high as seen in Figure 6. The HALT state is interrupted by the INTR signal just after CPU went into HALT state.
Before looking at the third way let's look closer at T2L@1 signal. Basically it's 8-input NOR which result is put down by RESET, HLT_HLD@1 and by T1@1, T1H@1, T3@1,T4@1R,T5@1,T6@1. Well T4@1R is T4@1 which is low when RESET is high (part of T5 schematic see below). So it basically doesn't matter if there is T4@1 or T4@1R there.
T4@1R is probably preferred because of the physical layout of the chip. It is just close the right place. T1H@1 is in fact T1@1 which is low when /HLT_HLD@-2 is low (part of T2 schematic see below). The reason why there is T1H@1 there is unknown to me. If we simulate the chip with polysilicon with this signal cut it works equally.
The only difference is slightly different timing of T2L@1 because T1H@1 is slightly delayed compared to T1@1 but this change in fact doesn't affect anything.
So T2L@1 is normally high during T2@1 as T2@1 is the only T*@1 signal which is not input of that NOR. It is high as well when no other T*@1 signal is high, i.e. during HOLD state, during WAIT state (see below) but not during HALT state as it is prevented by signal HLT_HLD@1. The same is true for RESET state, T2L@1 is low.
The T2L@1 signal is used for creating T3 signal - see below.
So the third way is used when CPU goes out of HOLD state. It is apparent from Figure 4. /HADR_EN must be high, T2L@1 must be high (to differentiate this situation from HALT state) and HLD must be low to signalize that HOLD state has just finished.

T2 signal

Schematic with FETs.

T2 signal is created from the T1 signal it is just postponed by two phases. If the CPU is going into HALT state (indicated by going /HLT_HLD@-2 down) the T2 signal is not created and CPU stops.
Before we look at the T3 signal we have to look at additional ROMs as they are part of the READY pad logic.

Instruction groups ROM

Schematic with FETs.

Basically this ROM creates groups of intructions which are later used in conjuction with timing ROMs for creating control signals.
In the schematic above is only a part of the ROM. The listing of the whole ROM is here. Read it now before you continue. The order of the signals is the same as in the real chip.

Additional timing signals for ROMs

Schematic with FETs.

These additional signals are used for timing ROMs. They can identify a single state (when two of them combined) or two states when used solely. You can see their use in practice below, under the schematic of register timing ROM.

Other additional timing signals for ROMs (part 1)

Schematic with FETs.

These signals are used in register timing ROM only, their purpose is to save some transistors. As understood from previous paragraph additional timing signals for T states can be used to identify either single T state or two T states (in practice successive two).
If we need to identify more T states (and in different cycles) it is sometimes easier to create special signal for that purpose.

Other additional timing signals for ROMs (part 2)

Schematic with FETs.

Second part of other additional timing signals.

Register timing ROM

Schematic with FETs.

This ROM tells each of the instruction group (to have some use for registers) when some action should happen.
In the schematic above is only a part of the ROM. The listing of the whole ROM is here. Read it now before you continue. The order of the signals is the same as in the real chip.

Register control ROM

Schematic with FETs.

This ROM tells what should be done for each instruction group in certain time the group and time are defined by the register timing ROM and instruction group ROM.
In the schematic above is only a part of the ROM. The listing of the whole ROM is here. Read it now before you continue. The order of the signals is the same as in the real chip. And that's why the outputs from the ROM are on the left side.

CYC_IDL signal

Schematic with FETs.

Figure 7 - CYC_IDL signal during ARHL instruction

CYC_IDL signalizes that current R1 or R2 cycle is a bus idle cycle i.e. no read or write takes place. Idle cycle can occur in R1 or R2 cycles only. See here for examples of instructions with idle cycles.
In the schematic above all circuits necessary for CYC_IDL generation are depicted. Part of the circuit is in fact part of the instruction groups ROM (/IGR_03, /IGR_04 and /IGR_35 signals), register timing ROM (RTR_06, RTR_10, RTR_11, RTR_42 and RTR_43 signals) and register control ROM (/NO_DREG_RWa signal).
You can see under what conditions are particular signals on if you follow particular ROM links.
CYC_IDL signal is one phase ahead of real cycles just like CYC_* and T* signals. For better orientation see following table:

Table 3

TIME			INSTRUCTION
cycle	state	phase	DAD	DSUB	RDEL	LDHI/LDSI	ARHL
M1	T1	PHI1
M1	T1	PHI2
M1	T2	PHI1
M1	T2	PHI2
M1	T3	PHI1
M1	T3	PHI2
M1	T4	PHI1
M1	T4	PHI2	RTR_42	RTR_42	RTR_42		RTR_42
R1	T1	PHI1	RTR_42	RTR_42	RTR_42		RTR_42
R1	T1	PHI2	FF	FF	FF		FF
R1	T2	PHI1	FF	FF	FF		FF
R1	T2	PHI2	NO_DREG_RW/FF	NO_DREG_RW/FF	NO_DREG_RW/FF		NO_DREG_RW/FF
R1	T3	PHI1	NO_DREG_RW/FF	NO_DREG_RW/FF	NO_DREG_RW/FF		NO_DREG_RW/FF
R1	T3	PHI2	RTR_10	RTR_10	RTR_10	RTR_10
R2	T1	PHI1	RTR_10	RTR_10	RTR_10	RTR_10	N/A
R2	T1	PHI2	NO_DREG_RW	NO_DREG_RW	NO_DREG_RW	NO_DREG_RW	N/A
R2	T2	PHI1	NO_DREG_RW	NO_DREG_RW	NO_DREG_RW	NO_DREG_RW	N/A
R2	T2	PHI2	NO_DREG_RW	NO_DREG_RW	NO_DREG_RW	NO_DREG_RW	N/A
R2	T3	PHI1	NO_DREG_RW	NO_DREG_RW	NO_DREG_RW	NO_DREG_RW	N/A
R2	T3	PHI2					N/A

Pink color means idle cycle. The text inside each box shows which signal is responsible for CYC_IDL being high. FF means that RTR_42 value is retained by subsequent flip-flop.
Note that the signal names shown in the table 3 describe that particular signal is responsible for CYC_IDL being high. This doesn't mean that this responsible signal is hith at that exact time - as shown in the schematic above this source signals are passed thru PHI1 and than thru PHI2 so they are delayed by two phases in the end.
On the other hand - in figure 7 the source signals RTR_42, RTR_42_FF (named FF in the table 3) and NO_DREG_RW are shown before they are passed thru PHI* signals so their timing is different than shown in the table 3.
NO_DREG_RW signal is used further in register control logic, it will be described later.
Note that if CYC_IDL is not prematurely forced low by CYC_M1 and T1 it would be one state too long.

READY pad and RDY_REAL signal

Schematic with FETs.

Figure 8 - READY pad and RDY_REAL signal during DAD instruction

READY pad is scanned during PHI1 of T2. If it is low during end of PHI1 of T2 a WAIT state is performed. So when RDY_REAL signal is low it prevents CPU from going into T3 state.
Once RDY_REAL goes low READY pad is scanned every PHI1 and RDY_REAL eventually goes back up. Again at the end of that PHI1 if READY is still low another WAIT state is performed.
RDI_REAL can be prevented from going low by CYC_IDL - i.e. in idle cycles CPU cannot be in WAIT state. The same is true for M1 cycle of TRAP or RST*.5 which are in fact idle cycles as well as RST instruction is performed internally and is not fetched.
This is indicated by INS_RST_TRP signal, which is high when TRAP and RST*.5 is being performed. It is low during normal INTR interrupt.
Note that M1 of normal interrupt (invoked by INTR pad) is not an idle cycle as instruction is fetched for real here.
In the figure 8 you can see M1 and R1 cycles of DAD instruction. R1 cycle is an idle cycle so READY pad going low has no effect and there is no WAIT state. Observe RDY_REAL_P and RDY_REAL_N signals which are inputs of super buffer and outputs from the flip flop.
When CYC_IDL is high and READY is low during PHI1 of T2 both inputs of NOR flip-flop are high. Which means that both outputs (RDY_REAL_P and RDY_REAL_N) are low for maximally one (PHI1) phase.
But is has no effect on the RDY_REAL signal as the super buffer's pull-up is most probably a depletion FET so it conducts anyhow. And even if it was an enhanced FET the output from the super buffer would float and all other consequent FETs remember last (high) value.
As well look at the behavior of the T2L@1 signal mentioned above as it is used in creation of T3 state.

T3 signal

Schematic with FETs.

This part is quite easy. T3 state is created when T2L@1 is high. Which is high when no T1 or T3 to T6 state is on. So it in normal case supplies T2 state. But RDY_REAL must be high too, which means that when CPU is in WAIT state no T3 state is created.
And of course /HADR_EN must be low, because T2L@1 is high as well in HOLD state and in this case T3 must be prevented from creation too. Look at the figure 8 where are two examples of T3 creation. See T2L@1 signal and think how each signal is passed thru PHI1 or PHI2.

T4 signal

Schematic with FETs.

This part is easy too. In fact T3 is passed thru PHI1 and thru PHI2 and thus delayed by one state. And of course CYC_M1 must be high as T4 occurs in M1 cycle only.

T5 signal

Schematic with FETs.

Here, again T4 is passed thru PHI1 and PHI2 and thus postponed by one state. And of course /INS_LNG must be low as T5 occurs only in long M1 cycles. And RESET can prevent T5 from creation.

T6 signal

Schematic with FETs.

And once more, T5 is passed thru PHI1 and PHI2 and thus postponed by one state.

5. Control bus and high address bus

A8 to A15 pads

Schematic with FETs.

Here we can see how A8 is tri-stated. The plus sign in NORs mean that they are in fact super NORs. The upper super NOR has two outputs, the one going out from the middle of it means that this output goes from the first stage of super NOR, i.e. from normal NOR.
This arrangement with two complementary enable signals is probably of some newer revision of 8085. In the picture of older revisions we can see only one enable signal and thus the whole circuit is simpler.
The analogical schematic is valid for A9 to A15 pads too. AB_8 to AB_15 signals are address bus and those go out from the register file which will be shown later.

ALE pad

Schematic with FETs.

If we look at the input, it is obvoius that ALE is high at T1, PHI1 (well in fact /PHI2 which has wider duty cycle than PHI1) and when CYC_IDL is low i.e. reading or writing takes place.
There is tri-state logic which is made inactive by putting it to Vcc. There was no tri-state logic in older revisions nor Intel manual says anything about ALE getting tri-stated.
This tri-state logic should probably not have used HADR_EN and /HADR_EN signals as the inverter for making complementary enable pair is in place and the input is quite near to CYC_IDL. Maybe the idea was to tri-state ALE in CYC_IDL cycles and it was later abandoned.
From this schematic is obvious that ALE gets high when CPU goes into HALT state, i.e. at PHI1 of second T1 state of HLT instruction just before buses get tri-stated. The address of instruction following HLT is put on address bus for one state but nothing is read nor written.

CYC_WR signal

Schematic with FETs.

CYC_WR signal is high when CYC_W1 or CYC_W2 is high and CPU is writing. There are 3 instructions which read during write cycle (IN, LHLD, and LDA) as shown here.
Before we look at other control bus pads let's recap when and how these pads are set. TS in table below means third state.

Table 4

ACTION	/RD	/WR	S0	S1	IO/M	/INTA
opcode fetch	0	1	1	1	0	1
memory read	0	1	0	1	0	1
memory write	1	0	1	0	0	1
I/O read	0	1	0	1	1	1
I/O write	1	0	1	0	1	1
idle cycle	1	1	0	1	0	1
int fetch / mem rd	1	1	1	1	1	0
interrupt idle cycle	1	1	1	1	1	1
halt state	TS	TS	0	0	TS	1

/WR pad

Schematic with FETs.

/WR pad uses the same enable logic as A8 pad. It is active in logic zero. Its activity is controlled by /CYC_WR signal, i.e. it is active in W1 and W2 cycle with exceptions explained above.
Signal /RD_WR_ON tells when the /WR or /RD pad should be active. It is output of a flip-flop. The interval starts in PHI1 of T2 and lasts for 3 phases as it is interrupted at PHI2 of T3 state.
Note that T3 signal has to be passed thru PHI1 and thus delayed by one phase so that it is aligned with T3 state as it is one phase ahead. T2 signal doesn't need to be delayed as PHI2 phase is common for both T2 signal and T2 state.

/RD pad

Schematic with FETs.

IN_OUT_W1 signal is high during cycle W1 of IN or OUT instructions, i.e. when data are read from or written to I/O port.
INT_MRI (INTerrupt Memory Read or interrupt Idle cycle) signal is high when interrupt instruction is being performed and anything is read from memory. This is true for normal interrupt (INTR). Usually one-byte instruction like RST 7 is fetched, but instructions like CALL addr can be used as well.
Note that even for R1 cycle of instructions like MOV A,M (during and interrupt fetch of course) this signal is high too. And of course INT_MRI is high during hidden opcode fetch cycle of TRAP or RST as the opcode (RST instruction) is created internally and not fetched in this case.
Timing of /RD pad uses the same signal as /WR pad does - /RD_WR_ON. The /RD pad is active (low) only when something is actually read from memory or I/O - i.e. no CYC_WR or CYC_IDL is active. And it is inactive as well in situation when reading is a memory read during performing interrupt instruction.
For example if interrupt instruction is LDA addr it is inactive for all four cycles (M1, R1, R2 and W1) of this instruction. If the instruction is IN addr it is inactive (high) for the first two (M1 and R2) cycles and active (low) for the last one (W1).

IO/M pad

Schematic with FETs.

Basically IO/M gets high when there is an IO read or write (during W1 cycle of IN or OUT instruction) or when there is a memory read during interrupt instruction or during M1 (hidden opcode fetch) of TRAP or RST. As the input signals are passed thru PHI1 it is clear that IO/M is aligned with the whole CPU cycle.

S1 pad

Schematic with FETs.

INS_INT signal is created here and is used elsewhere that's why it is an output signal here.
/HLT_NOINT signal shows that CPU is in HALT state. When an interrupt comes it makes the signal immediately inactive.
From the schematic it is obvious that S1 goes low when CPU is in HALT state or it is performing a write cycle. CYC_M1 seems to be little bit superfluous here as /CYC_WR never goes low when CYC_M1 is high.
The intermediate signal is passed thru T1 as /HLT_NOINT is not aligned with it. And of course as /HLT_NOINT could be low for a very long time and T1 is low as well in that case the state of S1 must be saved in a register.

S0 pad

Schematic with FETs.

Here we can see that S0 goes low when /HLT_NOINT is low exactly in the same way as S1 does. Therefore the intermediate signal is passed thru T1 and there is a need of a register for saving S0 state during long HALT state.
The other conditions which can put S0 low are CYC_M1 low and CYC_WR low and INT_MRI low. I.e. no opcode fetch, no memory write, no interrupt memory read and no interrupt idle cycle.

6. Register file

Register file part 1 (8 bit access)

Schematic with FETs.

As the schematic of register file is too complex I had to divide it into two parts. This is part one. It contains 4 out of 6 register pairs - PC, SP, WZ and BC. The other two - HL and DE are shown in the other part. Another registers like A, TMP and ACT are part of ALU, not part of the register file.
The schematic shows only the lowest 4 bits, those belong to low registers - PCL, SPL, Z, C, E and L. There are 16 bits together in the register file, all of them are the same. Well with only two small differences - low and high registers are controlled by different read and write signals.
As you can see all bits are implemented as 6T static memory cells. There are signals which activate particular register pair and connect them to read/write bus consisting of signals REG_B0, /REG_B0, REG_B1, /REG_B1 to REG_B15, /REG_B15.
So signal REG_PC_RW connects PC register pair to read/write bus, SEG_SP_RW does the same thing for SP register pair, REG_WZ_RW for WZ pair and REG_BC_RW for BC register pair.
When the register pair is connected to read/write bus its lower or higher part could be written to or read from the data bus. Signal LREG_WR stores the what is on data bus to selected low register (PCL, SPL, Z, C, E or H). Signal HREG_WR (not shown in the schematic) stores the what is on data bus to selected low register (PCH, SPH, W, B, D or H).
On the other hand signal /LREG_RD (active when low) copies the content of selected low register to data bus and similarly /HREG_RD (not shown in the schematic) does the analogical thing with selected high register.
There are many amplifiers in the read part as the result signal has to drive all data bus and all transistors connected to it. It is better to look at its schematic with FETs.

For better understanding of timing of the registers see the following figure and table where the behaviour of MOV C,B instruction will be shown.
Table 5 shows how data from register B go to register C in instruction MOV C,B (preceded and followd by a NOP). All values are sampled at the end of the particular PHI* phase.
We can see that data from register B are put on data bus (DB) in clock 5 PHI2. Data bus is not a register but when it gets isolated it can remember the last value put on it for a while.
So in the next cycle (clock 6 PHI1) the data are copied from the data bus to register TMP. The question is - why the data are not copied to the TMP register in the same clock/phase as it is read from the register file? Well, my theory is that the reason is that the reading of the data from the register file is a time consuming task.
See at the figure 9 - the data in fact get on the data bus relatively late, just a little while before the end of PHI2 phase. On the other hand - copying data from TMP thru DB to C register happens in one clock/phase as writing into the register file is much faster.
All signals and values related to data transfer itself are marked magenta. All signals and values related to fetching of MOV C,B instruction are marked cyan. The question how the opcode 48 appeared on the data bus will be explained later.
The following table is a nice example of fetch - execute overlap. In fact the data transfer itself takes place when the next instruction (NOP) is being fetched.
As the input to instruction gropus ROM is passed thru /INS_LOAD (aligned with PHI1) the change of instruction in IR appears to decoding ROMS at the beginning of PHI2 of T3.
And as the output from register control ROM is passed thru PHI1 (to align T* and CYC_* signals with real states and cycles) it is obvious how register file control signals for any instruction could be generated as late as during PHI2 of T3 of the next instruction.

Table 5

TIME				SIGNALS										REGISTERS					ACTION
clock	instruction	state	phase	REG_BC_RW	/HREG_RD	LREG_WR	TMP_FROM_DB	/ALU_TO_DB	INS_LOAD	T1	T2	T3	T4	B	C	TMP	DB	IR	external	internal
1	MOV C,B	T1	PHI1	0	1	0	0	1	0	1	0	0	0	C3	00	00	00	00
1	MOV C,B	T1	PHI2	0	1	0	0	1	0	0	1	0	0	C3	00	00	00	00
2	MOV C,B	T2	PHI1	0	1	0	0	1	0	0	1	0	0	C3	00	00	00	00	OF
2	MOV C,B	T2	PHI2	0	1	0	0	1	0	0	0	1	0	C3	00	00	00	00	OF
3	MOV C,B	T3	PHI1	0	1	0	0	1	1	0	0	1	0	C3	00	00	48	48	OF	IR=DB
3	MOV C,B	T3	PHI2	0	1	0	0	0	0	0	0	0	1	C3	00	00	00	48
4	MOV C,B	T4	PHI1	0	1	0	0	1	0	0	0	0	1	C3	00	00	00	48
4	MOV C,B	T4	PHI2	0	1	0	0	1	0	1	0	0	0	C3	00	00	00	48
5	NOP	T1	PHI1	0	1	0	0	1	0	1	0	0	0	C3	00	00	00	48
5	NOP	T1	PHI2	1	0	0	0	1	0	0	1	0	0	C3	00	00	C3	48		DB=B
6	NOP	T2	PHI1	0	1	0	1	1	0	0	1	0	0	C3	00	C3	C3	48	OF	TMP=DB
6	NOP	T2	PHI2	0	1	0	0	1	0	0	0	1	0	C3	00	C3	C3	48	OF
7	NOP	T3	PHI1	0	1	0	0	1	1	0	0	1	0	C3	00	C3	00	00	OF	IR=DB
7	NOP	T3	PHI2	1	1	1	0	0	0	0	0	0	1	C3	C3	C3	C3	00		C=DB=TMP
8	NOP	T4	PHI1	0	1	0	0	1	0	0	0	0	1	C3	C3	C3	00	00
8	NOP	T4	PHI2	0	1	0	0	1	0	1	0	0	0	C3	C3	C3	00	00

In the following figure TMP_0 means bit 0 of TMP register, IR_3 means bit 3 of IR register and analogically REG_C_0 is bit 0 for register C. Note how long it takes for bit DB_0 to change after REG_BC_RW and /HREG_RD signals get active.
OF means Opcode Fetch.

Figure 9 - Control signals of register file during the MOB C,B instruction

Register file part 2 (16 bit access)

Schematic with FETs.

Here is the second part of register file. Registers HL and DE are shown here. Note that these registers can be swapped by XCHG instruction. In that case the data stay at the same place but the CPU instead of accessing HL register starts to access DE register and vice versa.
The naming convention of HL/DE registers was chosen so because HL register contains HL content after the start of the simulator. The information if HL register cointains HL content of DE content and similarly DE register contains DE content or HL content is stored in a flip-flop.
Content of this flip flop is not changed by reset signal. Its schematic will be shown later.
Signals DREG_RD and /DREG_RD (they are complementary) copy the content of a register pair specified by corresponding REG_*_RW signal to the address latch . Address latch is directly attached to address bus. That is reason why during some 16 bit operations a garbage may be shown on AD0-AD7 and A8-A15 during T4-T6.
Besides that the address latch is connected to an incrementer/decrementer. Incrementer/decrementer is controlled by 4 signals. /DREG_CNT signal (active in zero) tells if incrementer/decrementer should increment/decrement (when /DREG_CNT is low) or do nothing (when /DREG_CNT is high).
When DREG_CNT2 is high (together with /DREG_CNT low) the incrementer/decrementer increments/decrements by 2. In fact only incrementing by 2 is used. It is used to increment PC by 2 in conditional jumps/calls when the condition is not met and thus save one machine cycle (and 3 T states).
Combination when both DREG_CNT2 and /DREG_CNT are high never occurs and doesn't do much useful things anyway.
Signals DREG_INC and DREG_DEC are complementary, so they never have the same value. They tell the incrementer/decrementer if it should increment (DREG_INC high, DREG_DEC low) or decrement (DREG_INC low and DREG_DEC high).
DREG_INC and DREG_DEC are ignored when /DREG_CNT is high.
The result from incrementer/decrementer could be copied back to any register pair when DREG_WR signal is high and particular register pair is selected by corresponding REG_*_RW signal high.
The output carry signal from the last stage of the incrementer/decrementer CNT_CY15. It is copied to K flag after INX, DCX instructions.

For better understanding of function of incrementer/decrementer see the following figure and table where the behaviour of DCX H instruction will be shown.

... table and figure should be added here ...

7. Register control signals

DREG_DEC and DREG_INC signals

Schematic with FETs.

DREG_DEC signal tells the incrementer/decrementer that it should decrement. It is postponed by one phase to aligned with access to registers which happens at PHI2. The incrementer/decrementer is normally set to increment. It decrements in following cases:
- In M1T4P2-M1T6P1 of DCX. It decrements particular double register.
- In M1T4P2-M1T6P1 and W1T1P2-W1T3P1 of PUSH, CALL and RST and of Ccc and RSTV when condition is met. It twice decrements SP register.
- In M1T4P2-M1T6P1 of Ccc and RSTV when the condition is not met. It does not do anything then.
- In W1T1P2-W1T3P1 of XTHL where it decrements SP register back to its original value after previous incrementing.
- In M1T4P2-R1T1P1 of XTHL where it does not do anything.

DREG_CNT2 signal

Schematic with FETs.

DREG_DEC signal tells the incrementer/decrementer that it should increment or decrement by two. In fact decrementing by two is never used, so it increments by two only. Incrementing by two is used in following case:
- In R1T1P1-R1T2P2 of Jcc, JNK, JK and Ccc when condition is not met. It icrements PC by two to skip the high byte of the target address which is not used and thus helps to speed those instructions by 3 cycles.

/DREG_CNT signal

Schematic with FETs.

/DREG_CNT signal tells the incrementer/decrementer whether it should increment/decrement (low) or whether it should remain the original value (high). Counting is supressed in following cases:
- In M1T4P1-M1T5P2 of SPHL and PCHL where in prevents the content of HL to change before copying into its target.
- In M1T4P1-M1T4P2 of ALU M, INR M, DCR M, MOV M,nonM2, MOV nonM1,M where it does not do anything.
- In R2T1P1-R2T2P2 of XTHL where it prevents SP from changing in R2. It increases in R1, does not change in R2 and decreases back in W1. It's increased in W2 but it's not written back.
- In M1T1P1-M1T2P2 of interrupt cycle where it prevents PC from incrementing because instruction is not fetched from [PC] position.

DREG_RD and /DREG_RD signals

Schematic with FETs.

DREG_RD and /DREG_RD signal put the content of selected double register to address latch, i.e. reads it. This happens every PHI2 of T3, T4 and T6. Reading is suppressed in following cases:
- In R2T3P2 of DAD, DSUB, RDEL, LDHI and LDSI - in those cases address latch containg last PC value needs to be preserved thru all R2 cycle as it cannot be re-read as the CPU is performing some other task.
- In R1T3P2 of ARHL - the reason from suppressing double register read is the same as in previous case.

DREG_WR signal

Schematic with FETs.

DREG_WR signal put the content of the address latch to the selected double register, i.e. writes to it. This happens every PHI2 of T2 and T5. Writing is suppressed in following cases:

REG_PC_RW signal

Schematic with FETs.

REG_PC_RW signal addresses the PC register allowing it to be read or written.

Work in progress... to be continued.