Intel 8085 Instruction Timing ROM

Intel 8085 instruction timing ROM

In my layers drawing instruction timing ROM occupies rectangle from 5713,1890 to 5972,3117. In the table below the content of the ROM is shown. Every 1 means a FET which can pull each column down. The table is in the same sequence as it is in the real chip.
Every column is a negated output signal which drives the instruction timing logic. Rows are inputs, i.e. when particular line (meaining instruction) is high every FET in that line pulls the corresponding column down.
Every instruction consists of 1 to 5 cycles. The first cycle is called M1 and consists of 4 or 6 states. In the M1 cycle opcode is fetched. Any other cycle consists of 3 states.
Other cycles are called R1 and R2 (CPU usually reads during these - exceptions DAD, DSUB, RDEL, LDHI, LDSI, ARHL) and W1 and W2 (CPU usualy writes during these - exceptions LDA, LHLD, IN).
Normal order of cycles is M1 R1 R2 W1 W2. Either R1 or both R1 and R2 cycles could be omitted. Whole sequence could be stopped after any cycle and next instruction is fetched.
Conditional instructions (Jcc, Ccc, Rcc, JNK, JK, RSTV) are ended prematurely when condition is not met. This feature is not covered in the table below, it is solved in the instruction timing logic.

All signals are active in 0 and describe current instruction in instruction register.
/INS_SKP_Rx signal says that both R1 and R2 cycles should be skipped.
/INS_SKP_R1 signal says that R1 cycle should be skipped. /INS_SKP_Rx and /INS_SKP_R1 are never active at the same time.
/INS_LNG signal says that M1 cycle should be 6 states long.
/INS_E1, /INS_E2 and /INS_E3 signals determine when cycle sequence should be stopped. The list of all existing combinations and their meaning is here:

/INS_E1	/INS_E2	/INS_E3	last cycle
1	1	1	M1
1	1	0	W1
1	0	1	R2
1	0	0	R1
0	1	1	W2

Here is the content of the ROM. 1 means that there is a FET while 0 means nothing is there. Do not forget that FET here means a pull-down so in fact 1 means FET which means output zero and vice versa.
- # states does not mention premature ending of conditional instructions
- in read cycles usually an argument, data or stack read takes place, exceptions are DAD, DSUB, RDEL, LDHI, LDSI and ARHL where bus idle cycles is performed instead (marked with red color)
- in write cycles usually a data or stack write takes place, exceptions are LDA, LHLD and IN where data read is performed instead (marked with blue color)

	/INS_SKP_Rx	/INS_SKP_R1	/INS_LNG	/INS_E1	/INS_E2	/INS_E3	# states	cycles
DI, EI	0	0	0	0	0	0	4	M1
ALU nonM2	0	0	0	0	0	0	4	M1
ALU imm	0	0	0	0	1	1	7	M1 R1
RIM, SIM	0	0	0	0	0	0	4	M1
ALU M	0	0	0	0	1	1	7	M1 R1
RST x	1	0	1	1	0	0	12	M1 W1 W2
DAA, CMA, STC, CMC	0	0	0	0	0	0	4	M1
RSTV	1	0	1	1	0	0	12	M1 W1 W2

STA	0	0	0	0	0	1	13	M1 R1 R2 W1
LDA	0	0	0	0	0	1	13	M1 R1 R2 W1
SHLX	1	0	0	1	0	0	10	M1 W1 W2
LHLX	0	0	0	0	1	0	10	M1 R1 R2
SHLD	0	0	0	1	0	0	16	M1 R1 R2 W1 W2
LHLD	0	0	0	1	0	0	16	M1 R1 R2 W1 W2
MVI nonM1	0	0	0	0	1	1	7	M1 R1
IN	0	1	0	0	0	1	10	M1 R2 W1

MVI M	0	1	0	0	0	1	10	M1 R2 W1
OUT	0	1	0	0	0	1	10	M1 R2 W1
RET	0	0	0	0	1	0	10	M1 R1 R2
Rcc	0	0	1	0	1	0	12	M1 R1 R2
DAD	0	0	0	0	1	0	10	M1 R1 R2
DSUB	0	0	0	0	1	0	10	M1 R1 R2
RDEL	0	0	0	0	1	0	10	M1 R1 R2
LDHI, LDSI	0	0	0	0	1	0	10	M1 R1 R2

ARHL	0	0	0	0	1	1	7	M1 R1
RLC, RRC, RAL, RAR	0	0	0	0	0	0	4	M1
PUSH	1	0	1	1	0	0	12	M1 W1 W2
POP	0	0	0	0	1	0	10	M1 R1 R2
SPHL	0	0	1	0	0	0	6	M1
Jcc	0	0	0	0	1	0	10	M1 R1 R2
JMP	0	0	0	0	1	0	10	M1 R1 R2
JNK, JK	0	0	0	0	1	0	10	M1 R1 R2

PCHL	0	0	1	0	0	0	6	M1
Ccc	0	0	1	1	0	0	18	M1 R1 R2 W1 W2
CALL	0	0	1	1	0	0	18	M1 R1 R2 W1 W2
XTHL	0	0	0	1	0	0	16	M1 R1 R2 W1 W2
INX	0	0	1	0	0	0	6	M1
DCX	0	0	1	0	0	0	6	M1
INR nonM1, DCR nonM1	0	0	0	0	0	0	4	M1
INR M, DCR M	0	1	0	0	0	1	10	M1 R2 W1

STAX	1	0	0	0	0	1	7	M1 W1
LDAX	0	0	0	0	1	1	7	M1 R1
LXI	0	0	0	0	1	0	10	M1 R1 R2
MOV M,nonM2	1	0	0	0	0	1	7	M1 W1
MOV nonM1,M	0	0	0	0	1	1	7	M1 R1
MOV nonM1,nonM2	0	0	0	0	0	0	4	M1
XCHG	0	0	0	0	0	0	4	M1
HLT	0	0	0	0	0	0	5	M1