65CE02 ROM (PLA)

65CE02 PLA consists as expected from OR plane and AND plane. In the table below the rows and columns are transponed compared to the real chip so that they better fit to the table. But generally if we ignore the transposition, the order of the data is the same as in the real chip. As well first three columns are not shown as they are dummy and do not code anything. The content of the table was taken from 65CE02R2 published on this page: http://www.siliconpr0n.org/. The redrawed chip is shown here: http://www.pastraiser.com/pictures/65CE02/layers/Total.png. Although the content of the ROM is taken from revision 2 of the chip I suppose that revision 1 has the same content.
Inputs to the AND plane are instruction register (IR) and its negation and 6 timing signals T2 - T7. Note that T1 is not necessary because nothing but fetch of the instruction during T1P2 happens. Of course T1 overlaps with the last cycle of the previous instructions. Some of the signals are delayed by one or two clock phases (as explained below the table). That's the reason how some instructions like BRK can pospone its SYNC signal into T8 cycle which overlaps with T1 of the next instruction. The output from the ROM takes place in P1 of corresponding T cycle. During P2 the ROM gets precharged, i.e. all inputs are high.
In the Bitmask column bitmask for the sake of simplicity is shown. "x" instead of 0 or 1 means don't-care bit. Last position of the bitmask is the number of the corresponding T cycle. In Instruction(s) column there is list of instructions coded by each column (note that because of the transposition it is a row of the table in fact). If the column codes more than 4 instructions there is no space for it and only "Too many(x)" is stated instead there with "x" showing how many instructions. But if you hover over this statement with the mouse pointer for a while the tooltip with a complete list of respective instructions should emerge.
In the AND plane the row00 - row41 represents real rows in the chip (due to the transposition they are columns in the table). If there is a transistor in some row/column crossing it creates a ROM output signal. It's number is shown in a corresponding place. If you hover over the number with the mouse pointer a tooltip with name of the signal and short explanation of it emerges. Further explanation is given below the table.

AND planeBitmaskInstruction(s)OR plane
 Column
 /IR0
 IR0
 /IR1
 IR1
 /IR2
 IR2
 /IR3
 IR3
 /IR4
 IR4
 /IR5
 IR5
 /IR6
 IR6
 /IR7
 IR7
 T2
 T3
 T4
 T5
 T6
 T7
 row00
 row01
 row02
 row03
 row04
 row05
 row06
 row07
 row08
 row09
 row10
 row11
 row12
 row13
 row14
 row15
 row16
 row17
 row18
 row19
 row20
 row21
 row22
 row23
 row24
 row25
 row26
 row27
 row28
 row29
 row30
 row31
 row32
 row33
 row34
 row35
 row36
 row37
 row38
 row39
 row40
 row41
000   X X          X     xxxx x11x 2Too many (64)            08                             
001 X   X          X     xxxx x1x1 2Too many (64)            08                             
002     X      X   X     x0xx x1xx 2Too many (64)            08                             
003 XX   X         X     xxxx 0x01 2Too many (32) 32          08                             
004     XX X       X     xxx0 01xx 2Too many (32) 32          08                             
005     XX   X     X     xx0x 01xx 2Too many (32) 32          08                             
006     XX     X   X     x0xx 01xx 2Too many (32) 32                                        
007 X XX  X XX  XX X     0101 1011 2 TAB56             02                           
008X X X X X X X X X     0000 0000 2 BRK            08                24 2707         
009 X XX  X X X XX X     0111 1011 2 TBA  51                     37 34   00           
010X X  XX  XX X X   X   0001 0100 4 TRB a8                19                    22    
011X X  X X XX X X    X  0001 1100 5 TRB a16                19                    22    
012 X X XX          X    xxxx 0111 3Too many (16) 32 54                           27      30   
013 X X X X         X    xxxx 1111 3Too many (16)                19                     30   
014 XX X X           X   xxxx 0001 4Too many (16)     04                        05           
015X  XX X  X        X   xxx1 0010 4Too many (8)     04        16     13         05           
016X  XX X X X X  X   X  1000 0010 5 STA (r8,SP),Y     04        16     13         0527          
017X  XX X X  X X X   X  1110 0010 5 LDA (r8,SP),Y     04        16     13         05           
018 X X X            X   xxxx x111 4Too many (32)                              25           
019 X X X          X     xxxx x111 2Too many (32) 32                                        
020 XX X X    X X     X  x11x 0001 5 ADC (a8,X); ADC (a8),Y; SBC (a8,X); SBC (a8),Y     237312      16  62                        
021 XX  XX    X X   X    x11x 0101 3 ADC a8; ADC a8,X; SBC a8; SBC a8,X     237312      16  62                        
022 XX  X X   X X    X   x11x 1101 4 ADC a16; ADC a16,X; SBC a16; SBC a16,X     237312      16  62                        
023 XX    X X X X    X   x111 1x01 4 ADC a16,Y; ADC a16,X; SBC a16,Y; SBC a16,X     237312      16  62                        
024 XX X  XX  X X  X     x110 1001 2 ADC #d8; SBC #d8     237312      16  62                        
025X  XX X  X X X     X  x111 0010 5 ADC (a8),Z; SBC (a8),Z     237312      16  62                        
026 XX X X       X    X  0xxx 0001 5Too many (8)56 51  29                  37 34   25           
027     X X       XX     1xxx 11xx 2Too many (32)            08                             
028 XX  XX       X  X    0xxx 0101 3Too many (8)56 51  29                  37 34   25           
029     X X   X    X     xx1x 11xx 2Too many (32)            08                             
030X  XX X X  X XX      X0110 0010 7 RTN              16    391306        25           
031 X XX  XX  XX X X     0010 1011 2 TYS                     06          50         
032 X XX X  X   X X X    11x1 0011 3 BNE r16; BEQ r16     29    10   16     13 21    58  25       41   
033 X XX X  X   XX  X    01x1 0011 3 BVC r16; BVS r16     29    10   16   61 13 21       25       41   
034 X XX X   X X  X X    100x 0011 3 BRU r16; BCC r16     29    10   16     13 21       25       41   
035 X XX X  X  X  X X    10x1 0011 3 BCC r16; BCS r16     29  71 10   16     13 21       25       41   
036 X XX X  X  X X  X    00x1 0011 3 BPL r16; BMI r16     29    10   16     13 21  59    25       41   
037X X X X X  X XX   X   0110 0000 4 RTS          10   16     13         25           
038X X  X X   X XX    X  011x 1100 5 JMP (a16); JMP (a16,X)          10                   25           
039   XX X X  XX X      X0010 001x 7 JSR (a16); JSR (a16,X)          10                   25           
040X  XX X X  X XX    X  0110 0010 5 RTN 32        10   16     13                     
041 X XX X X  X XX    X  0110 0011 5 BSR r16     29    10           21       25       41   
042X X X X X X  XX    X  0100 0000 5 RTI          10                   25           
043X X X X X  XX X    X  0010 0000 5 JSR a16          10                   25       41   
044X X  X XX X  XX  X    0100 1100 3 JMP a16          10                   25       41   
045X X X X X X X X      X0000 0000 7 BRK          10                   25           
046X  XX X  X       X    xxx1 0010 3Too many (8) 32   29   0333  3116                  48        
047 XX X X          X    xxxx 0001 3Too many (16) 32       0333  31                            
048X  XX X X  X XX     X 0110 0010 6 RTN 32   29        1647                       46  
049X  XX  X XX X  XX     1001 1010 2 TXS           53                           46  
050 X XX X  X      X     xxx1 0011 2Too many (8)     29    33   16      11 43                  
051 X XX X   X X  XX     100x 0011 2 BRU r16; BCC r16     29    33   16      11 43                  
052 X XX X X  X XX X     0110 0011 2 BSR r16     29    33   16      11 43     24 27          
053X  XX X X  X X X  X   1110 0010 4 LDA (r8,SP),Y 32   29    33  3116                 50         
054X  XX X X X X  X  X   1000 0010 4 STA (r8,SP),Y 32   29    33  3116                 50         
055 X XX X X    X X  X   11x0 0011 4 DEW a8; INW a8 32       03   31                            
056X X X X X  XX X X     0010 0000 2 JSR a16          33                  24 27          
057X X  X XX X  XX X     0100 1100 2 JMP a16          33                               
058 X X X X          X   xxxx 1111 4Too many (16)     29   0942   16      11 43    57             
059 XX  X X      X   X   0xxx 1101 4Too many (8)56 51  29                  37 34   25           
060 XX    X X    X   X   0xx1 1x01 4Too many (8)56 51  29                  37 34   25           
061 XX  X   X      X     xxx1 x101 2Too many (16)     29     53  16                           
062 XX    X X       X    xxx1 1x01 3Too many (16) 32  01         16     13                     
063X  X  X  X      X     xxx1 0x10 2Too many (16) 32          08                             
064 XX X X    X       X  xx1x 0001 5Too many (8)  51                     37 34   25           
065   X XX      X    X   x1xx 011x 4Too many (16)                              25           
066X  X X X         X    xxxx 1110 3Too many (16) 32  01                                     
067   X XX       X   X   0xxx 011x 4Too many (16)                              25           
068 XX X  XX     X X     0xx0 1001 2 ORA #d8; AND #d8; EOR #d8; ADC #d856 51  29                  37 34   25           
069X    X X       X X    1xxx 11x0 3Too many (16) 32  01                                     
070 XX X X X       X     xxx0 0001 2Too many (8)     29     53  16                           
071 XX  XX    X     X    xx1x 0101 3Too many (8)  51                     37 34   25           
072X    X X   X     X    xx1x 11x0 3Too many (16) 32  01                                     
073X  XX X  X    X    X  0xx1 0010 5 ORA (a8),Z; AND (a8),Z; EOR (a8),Z; ADC (a8),Z56 51  29                  37 34   25           
074X    X X    X    X    x0xx 11x0 3Too many (16) 32  01                                     
075 XX X  X X      X     xxx1 1001 2Too many (8)     29      08 16                 50         
076 XX  X X   X      X   xx1x 1101 4Too many (8)  51                     37 34   25           
077  X  XX   X  X X X    110x 010x 3 CPY a8; CMP a8; CPZ a8; CMP a8,X      73       16      11  37 34   25           
078 XX  X X         X    xxxx 1101 3Too many (16) 32  01                                     
079 XX    X X X      X   xx11 1x01 4Too many (8)  51                     37 34   25           
080X  X X   X   X  X     x1x1 x110 2Too many (8)     29     53  16                           
081 XX X X  X       X    xxx1 0001 3Too many (8)     29        16                 50         
082X  X X   X    X X     0xx1 x110 2Too many (8)     29     53  16                           
083  X  X X  X  X X  X   110x 110x 4 CPY a16; CMP a16; CPZ a16; CMP a16,X      73       16      11  37 34   25           
084X    X   X X  X X     0x11 x1x0 2Too many (8)     29     53  16                           
085  X  X   X XX   X     x011 x10x 2Too many (8)     29     53  16                           
086X    XX  X   XX X     01x1 01x0 2 ASR a8,X; LSR a8,X; STZ a8,X; ROR a8,X 32   29     5308 16                           
087X X X X  X   X XX     11x1 0000 2 BNE r8; BEQ r8     29   0942   16      11 43   58  25           
088X X X X  X   XX X     01x1 0000 2 BVC r8; BVS r8     29   0942   16   61  11 43      25           
089X X X X   X X  XX     100x 0000 2 BRU r8; BCC r8     29   0942   16      11 43      25           
090X X X X  X  X  XX     10x1 0000 2 BCC r8; BLS r8     29  710942   16      11 43      25           
091X X X X  X  X X X     00x1 0000 2 BPL r8; BMI r8     29   0942   16      11 43 59    25           
092X X X X X  X X XX     1110 0000 2 CPX #d8     2973  38 53  16      11  37 34   25           
093X X X X X X  X XX     1100 0000 2 CPY #d8     2973  38    16      11  37 34   25 50         
094X  X XX    X X X X    111x 0110 3 INC a8; INC a8,X 32 54          16      11  37 34    27          
095X  XX X X X  X XX     1100 0010 2 CPZ #d8     2973  38    16      11  37 34   25  48        
096X  X XX   X  X X X    110x 0110 3 DEC a8; DEC a8,X 32 54     38    16         37 34    27          
097 X    X X    X XX     11x0 0xx1 2Too many (8) 32          08                             
098X  X X X   X X X  X   111x 1110 4 INC a16; INC a16,X 32 54          17      11  37 34    27          
099X  X X X  X  X X  X   110x 1110 4 DEC a16; DEC a16,X 32 54     38    17         37 34    27          
100 XX X X   X  X X   X  110x 0001 5 CMP (a8,X); CMP (a8),Y      73       17      11  37 34   25           
101X X  XX    XX X  X    001x 0100 3 BIT a8; BIT a8,X56    28          1962      37 34   25           
102 X X   XX      XX     1xx0 1x11 2Too many (8)            08                             
103X  X X X XX     X     xx01 1110 2 ASL a16,X; LSR a16,X; STZ a16,X; DEC a16,X     28     53  17                           
104 X X XX       X  X    0xxx 0111 3Too many (8)         38      19                         
105X X  XX X  X X X X    1110 0100 3 CPX a8     2873  38 53  17      11  37 34   25           
106  X  XX  X  X  XX     10x1 010x 2 STY a8,X; STA a8,X; LDY a8,X; LDA a8,X     28     53  17                           
107X X  X X   XX X   X   001x 1100 4 BIT a16; BIT a16,X56    28           62      37 34   25           
108 X  X  X X  X  X X    10x1 10x1 3 STA a16,Y; STX a16,Y; LDA a16,Y; LDZ a16,X 32  01         17     13                     
109X X  X XX  X X X  X   1110 1100 4 CPX a16     2873  38 53  17      11  37 34   25           
110 XX    X XX  X X  X   1101 1x01 4 CMP a16,Y; CMP a16,X      73       17      11  37 34   25           
111 XX X X      X X   X  11xx 0001 5 CMP (a8,X); CMP (a8),Y; SBC (a8,X); SBC (a8),Y56    28   38                                
112 XX  XX      X X X    11xx 0101 3 CMP a8; CMP a8,X; SBC a8; SBC a8,X56    28   38                                
113X X  XX   X X X  X    000x 0100 3 TSB a8; TRB a85632   28          19         34    27          
114 XX  X X     X X  X   11xx 1101 4 CMP a16; CMP a16,X; SBC a16; SBC a16,X56    28   38                                
115X X  X X  X X X   X   000x 1100 4 TSB a16; TRB a165632   28          19         34    27          
116 X XX  XX      X X    1xx0 1011 3 STY a16,X; LDZ a16; ASW a16; ROW a16 32  01                                     
117 XX    X X   X X  X   11x1 1x01 4 CMP a16,Y; CMP a16,X; SBC a16,Y; SBC a16,X56    28   38                                
118X X  XX   X X X   X   000x 0100 4 TSB a8; TRB a856  54 28                        25           
119 XX X  XX X X  XX     1000 1001 2 BIT #d856    28          1962      37 34   25           
120X  X XX  X  X  XX     10x1 0110 2 STX a8,Y; LDX a8,Y     28        17                 50         
121 X  X X X  XX X X     0010 00x1 2 AND (a8,X); JSR (a16,X)     28     53  17                           
122X X  X X  X X X    X  000x 1100 5 TSB a16; TRB a1656  54 28                        25           
123 X  X  X XX X  XX     1001 10x1 2 STA a16,Y; STX a16,Y     28      08 17                 50         
124 XX X  XX    X XX     11x0 1001 2 CMP #d8; SBC #d856    28   38                                
125X  XX X  X   X X   X  11x1 0010 5 CMP (a8),Z; SBC (a8),Z56    28   38                                
126X  X X   X XX  XX     1011 x110 2 LDX a8,Y; LDX a16,Y     28        17                 50         
127   XX X X  XX X X     0010 001x 2 JSR (a16); JSR (a16,X)            08                24 27          
128X  XX X X  X X XX     1110 0010 2 LDA (r8,SP),Y     28      08 1747                          
129X  XX X X X X  XX     1000 0010 2 STA (r8,SP),Y     28      08 1747                          
130 X XX  X X XX  XX     1011 1011 2 LDZ a16,X     28     5308 17                           
131 X XX  XX X X  XX     1000 1011 2 STY a16,X     28     53  17                           
132X X  XX X X  X X X    1100 0100 3 CPY a8     28   38                      50         
133X X  XX  XX  X X X    1101 0100 3 CPZ a8     28   38                       48        
134X X  X XX X  X X  X   1100 1100 4 CPY a16     28   38                      50         
135X X  X X XX  X X  X   1101 1100 4 CPZ a16     28   38                       48        
136X  XX X X  X X X X    1110 0010 3 LDA (r8,SP),Y 32  0140        17    3913                     
137X  XX X X X X  X X    1000 0010 3 STA (r8,SP),Y 32  0140        17    3913                     
138   XX X X  XX X    X  0010 001x 5 JSR (a16); JSR (a16,X) 32  01                                     
139X  XX X X  X XX X     0110 0010 2 RTN     40      08          43                  
140X  XX X X  X XX  X    0110 0010 3 RTN    0140      45         21      24            
141 XX X  XX X  X XX     1100 1001 2 CMP #d8      73       17      11  37 34   25           
142X  X XX    XX  X X    101x 0110 3 LDX a8; LDX a8,Y                        37 34   25         55 
143X  X X X   XX  X  X   101x 1110 4 LDX a16; LDX a16,Y                        37 34   25         55 
144X X X  XX  X X XX     1110 1000 2 INX           53  17      11  37 34             55 
145X  XX  XX X  X XX     1100 1010 2 DEX         38 53  17         37 34             55 
146X  XX X X  XX  XX     1010 0010 2 LDX #d8                        37 34   26         55 
147X  XX  X X X X X X    1111 1010 3 PLX                        37 34   26         55 
148X  XX  XX  XX  XX     1010 1010 2 TAX56                       37 34             55 
149X  XX  X X XX  XX     1011 1010 2 TSX               47        37 34             55 
150X X  XX    XX  X X    101x 0100 3 LDY a8; LDY a8,X                        37 34   26          52
151X  XX X  XX  X X   X  1101 0010 5 CMP (a8),Z      73       17      11  37 34   26           
152X X  X X   XX  X  X   101x 1100 4 LDY a16; LDY a16,X                        37 34   26          52
153X  XX X X X  XX  X    0100 0010 3 NEG A56 51           17      11  37 34               
154X X X  XX X  X XX     1100 1000 2 INY              17      11  37 34     50        52
155X  XX  X XX X X X     0001 1010 2 INC A56 51           17      11  37 34               
156X  XX  X X XX X X     0011 1010 2 DEC A56 51      38    17         37 34               
157X X X  XX X X  XX     1000 1000 2 DEY         38    17         37 34     50        52
158X X X X X  XX  XX     1010 0000 2 LDY #d8                        37 34   26          52
159X  XX  X X X XX  X    0111 1010 3 PLY                        37 34   26          52
160 X XX X X  X X X X    1110 0011 3 INW a8 32 54          17      11         27          
161X X X  XX  XX  XX     1010 1000 2 TAY56                       37 34              52
162 X XX  XX X X X X     0000 1011 2 TSY                   39    37 34              52
163X X X X X  X XX  X    0110 0000 3 RTS          42 45 17      11       24            
164 X XX  X XX X X X     0001 1011 2 INZ    49         17      11  37 34      48        
165X  XX X X  X XX   X   0110 0010 4 RTN          42 45 17      11       24            
166X  XX X X X  XX X     0100 0010 2 NEG A56 51  40   38                    26      20    
167 X XX  X X XX X X     0011 1011 2 DEZ    49    38    17         37 34      48        
168 X XX X X X  X X X    1100 0011 3 DEW a8 32 54     38    17                27          
169 X  X X X X  X X   X  1100 00x1 5 CMP (a8,X); DEW a8         38                                
170X  X XX     X X  X    00xx 0110 3 ASL a8; ASL a8,X; ROL a8; ROL a8,X 32 54  73                 36 35    27  14       
171X  X X X    X X   X   00xx 1110 4 ASL a16; ASL a16,X; ROL a16; ROL a16,X 32 54  73                 36 35    27  14       
172X  XX  XX   X X X     00x0 1010 2 ASL A; ROL A56 51   73                 36 35       14       
173 X XX  X   XX  X  X   101x 1011 4 LDZ a16; LDZ a16,X    49                   36 35   26           
174 X XX X X  XX  XX     1010 0011 2 LDZ #d8    49                   36 35   26           
175 X XX  X X X X X X    1111 1011 3 PLZ    49                   36 35   26           
176 X XX  XX X  XX X     0100 1011 2 TAZ56   49                   36 35               
177 X XX  XX    X X  X   11x0 1011 4 ASW a16; ROW a16 32 54                           27  14       
178 X XX  XX    X X    X 11x0 1011 6 ASW a16; ROW a16 32 54  73             13   36 35    27  14 18     
179X X  XX   X  XX  X    010x 0100 3 ASR a8; ASR a8,X 32    73                        27  14       
180 X XX X X X  XX X     0100 0011 2 ASR A56    4073                       26   14       
181 XX X  XX  X    X     xx10 1001 2 AND #d8; ADC #d8; LDA #d8; SBC #d8  51                     36 35   26           
182X  X XX      XX  X    01xx 0110 3 LSR a8; LSR a8,X; ROR a8; ROR a8,X 32 54  73                 36 35    27   15      
183X  X X X     XX   X   01xx 1110 4 LSR a16; LSR a16,X; ROR a16; ROR a16,X 32 54  73                 36 35    27   15      
184 XX X X  X        X   xxx1 0001 4Too many (8)              17     13                     
185X  XX X  X X       X  xx11 0010 5 AND (a8),Z; ADC (a8),Z; LDA (a8),Z; SBC (a8),Z  51                     36 35   26           
186X  X X X X       X    xxx1 1110 3Too many (8)              17     13                     
187X  X X X     X     X  x1xx 1110 5Too many (8)                              26           
188X  X X X      X    X  0xxx 1110 5Too many (8)                              26           
189 X XX X X    X X   X  11x0 0011 5 DEW a8; INW a8 32 54          17     13   36 35    27    18     
190X  XX  XX    XX X     01x0 1010 2 LSR A; ROR A56 51   73                 36 35        15      
191X X  XX   X  XX   X   010x 0100 4 ASR a8; ASR a8,X   54  7312                36 35   26    15      
192 X X X X       X  X   1xxx 1111 4Too many (8)                   60                      
193X X X X  XX     X     xx01 0000 2 BPL r8; BVC r8; BCC r8; BNE r8                   60                      
194X    X X X X  X  X    0x11 11x0 3 BIT a16,X; ROL a16,X; JMP (a16,X); ROR a16,X              17     13                     
195X    X X X XX    X    x011 11x0 3 BIT a16,X; ROL a16,X; LDY a16,X; LDX a16,Y              17     13                     
196X    XX   X X  XX     100x 01x0 2 STY a8; STX a8; STY a8,X; STX a8,Y                               27          
197  X  XX   X X  XX     100x 010x 2 STY a8; STA a8; STY a8,X; STA a8,X                               27          
198 XX X X   X  XX    X  010x 0001 5 EOR (a8,X); EOR (a8),Y                                     20    
199 XX  XX   X  XX  X    010x 0101 3 EOR a8; EOR a8,X                                     20    
200 XX  X X  X  XX   X   010x 1101 4 EOR a16; EOR a16,X                                     20    
201 XX    X XX  XX   X   0101 1x01 4 EOR a16,Y; EOR a16,X                                     20    
202 XX X  XX X  XX X     0100 1001 2 EOR #d8                                     20    
203X  XX X  XX  XX    X  0101 0010 5 EOR (a8),Z                                     20    
204X X X X X   X X  X    00x0 0000 3 BRK; JSR a16   54                 4421      24 27          
205X  X XX    X  X  X    0x1x 0110 3 ROL a8; ROL a8,X; ROR a8; ROR a8,X       12                                  
206  X  X X XX  X    X   x101 110x 4 AUG; EOR a16,X; CPZ a16; CMP a16,X                              26           
207X    X X  X X  X X    100x 11x0 3 STY a16; STX a16; STZ a16; STZ a16,X                               27          
208 X XX X  XX      X    xx01 0011 3 BPL r16; BVC r16; BCC r16; BNE r16                   60                      
209X   X X X  XX X  X    0010 00x0 3 JSR a16; JSR (a16)   54                 4421      24 27          
210X  X XX   X X  X X    100x 0110 3 STX a8; STX a8,Y   54       53                  26           
211X  X X X   X  X   X   0x1x 1110 4 ROL a16; ROL a16,X; ROR a16; ROR a16,X       12                                  
212X X  XX    X XX  X    011x 0100 3 STZ a8; STZ a8,X   54                          26  48        
213X X  XX   X X  X X    100x 0100 3 STY a8; STY a8,X   54                          26 50         
214  X  X X  X X  X X    100x 110x 3 STY a16; STA a16; STZ a16; STA a16,X                               27          
215X X X  XX X   X X     0x00 1000 2 PHP; PHA     40                       24 27          
216 X XX  X  X X  X X    100x 1011 3 STY a16,X; STX a16,Y              17     13          27          
217 XX X X   X X  X   X  100x 0001 5 STA (a8,X); STA (a8),Y56  54                          26           
218X  XX  X XX  X  X     x101 1010 2 PHY; PHX     40                       24 27          
219X X X  XX  X XX  X    0110 1000 3 PLA  51                     36 35   26           
220 X XX X X  X  X  X    0x10 0011 3 JSR (a16,X); BSR r16   54                 4421      24 27          
221X X X X X    XX X     01x0 0000 2 RTI; RTS            45                24            
222 XX  XX   X X  X X    100x 0101 3 STA a8; STA a8,X56  54                          26           
223X X X  XX  X  X X     0x10 1000 2 PLP; PLA     40      45                24            
224X  XX  X X X X  X     x111 1010 2 PLY; PLX     40      45                24            
225 X   XX    XX X  X    001x 01x1 3 AND a8; RMB2 a8; AND a8,X; RMB3 a8                19                         
226  X  X X   XX X   X   001x 110x 4 BIT a16; AND a16; BIT a16,X; AND a16,X                19                         
227   XX  X XX  X XX     1101 101x 2 PHX; PHZ     40                       24 27          
228 XX  X X  X X  X  X   100x 1101 4 STA a16; STA a16,X56  54                          26           
229X  XX X X  X X X    X 1110 0010 6 LDA (r8,SP),Y  51                     36 35   26           
230X   X X X  XX X   X   0010 00x0 4 JSR a16; JSR (a16)   54                 44 43                  
231 X XX X X X  XX  X    0100 0011 3 ASR A56 51   7312                36 35        15      
232X  XX  XX X X  XX     1000 1010 2 TXA  51        53            36 35               
233X    X X XX X  X  X   1001 11x0 4 STZ a16; STZ a16,X   54                          26  48        
234 XX    X XX X  X  X   1001 1x01 4 STA a16,Y; STA a16,X56  54                          26           
235X  XX  XX  X  X X     0x10 1010 2 ROL A; ROR A       12                                  
236X X  XX    X XX X     011x 0100 2 STZ a8; STZ a8,X                               27          
237   XX  X X X X XX     1111 101x 2 PLX; PLZ     40      45                24            
238 X XX X X  X  X    X  0x10 0011 5 JSR (a16,X); BSR r16              17     13                     
239X X X  XX X  XX  X    0100 1000 3 PHA56  54                 44        26           
240 X XX X X  X  X   X   0x10 0011 4 JSR (a16,X); BSR r16   54                 44 43                  
241X X X  X XX X  XX     1001 1000 2 TYA  51                     36 35     50         
242X X  X   X X X X  X   1111 x100 4 PHW #d16; PHW a16   54                         24 27          
243 X XX X X    X X    X 11x0 0011 6 DEW a8; INW a8                              26           
244X X  X X   X XX   X   011x 1100 4 JMP (a16); JMP (a16,X) 32        42  31                            
245X  XX  X XX  X X X    1101 1010 3 PHX   54       53         44        26           
246 X XX  XX    X X     X11x0 1011 7 ASW a16; ROW a16                              26           
247X  XX  X XX  XX  X    0101 1010 3 PHY   54                 44        26 50         
248 X XX  XX    X X   X  11x0 1011 5 ASW a16; ROW a16 32           31                            
249 X XX  XX  X XX X     0110 1011 2 TZA  51                     36 35      48        
250 XX X X   X X  X  X   100x 0001 4 STA (a8,X); STA (a8),Y                               27          
251X X X  XX X X X  X    0000 1000 3 PHP   54     70           44        26           
252X X X X X X  XX  X    0100 0000 3 RTI    75       45                24            
253X X X X X X  XX   X   0100 0000 4 RTI          42 45                24            
254X  XX X X X X X X     0000 0010 2 CLE     40      67                 26           
255   XX X X  XX X     X 0010 001x 6 JSR (a16); JSR (a16,X) 32        42  31                            
256X X X  X X X XX X     0111 1000 2 SEI     40         64              26           
257X  XX X  XX X  X   X  1001 0010 5 STA (a8),Z56  54                          26           
258X X X  X XX  XX X     0101 1000 2 CLI     40        65               26           
259X X X X X X X X   X   0000 0000 4 BRK   54                 44 43     24 27          
260X  XX X X X X  X    X 1000 0010 6 STA (r8,SP),Y56  54                          26           
261 X XX  X XX  X X X    1101 1011 3 PHZ   54                 44        26  48        
262X X  X X X X X    X   x111 1100 4 JMP (a16,X); PHW a16             31                            
263X X X X X X X X     X 0000 0000 6 BRK 32        42  31 64                          
264 X XX X X X X X X     0000 0011 2 SEE     40       66                26           
265 XX X X    XX X    X  001x 0001 5 AND (a8,X); AND (a8),Y                19                         
266 X XX  XX X X  X  X   1000 1011 4 STY a16,X   54                          26 50         
267X X  XX  X X X XX     1111 0100 2 PHW #d16   54                         24 27          
268 XX    X XX X  X X    1001 1x01 3 STA a16,Y; STA a16,X                               27          
269X  X X XX X X  X  X   1000 1110 4 STX a16   54       53                  26           
270X X X  XX  XX X  X    0010 1000 3 PLP    75                         26           
271 X XX  X XX X  X  X   1001 1011 4 STX a16,Y   54       53                  26           
272X X  X XX X X  X  X   1000 1100 4 STY a16   54                          26 50         
273X X X X X X X X    X  0000 0000 5 BRK 32 54     70           44                    
274 XX    X X XX X   X   0011 1x01 4 AND a16,Y; AND a16,X                19                         
275X X X  X X X X XX     1111 1000 2 SED           68                              
276X X X  X XX  X XX     1101 1000 2 CLD          69                               
277X X  XX  X X X X   X  1111 0100 5 PHW #d16                     44        26           
278 XX X  XX  XX X X     0010 1001 2 AND #d8                19                         
279X  XX X  X XX X    X  0011 0010 5 AND (a8),Z                19                         
280X X X  X X XX  XX     1011 1000 2 CLV                63                         
281 X XX  XX  X X X  X   1110 1011 4 ROW a16       12                                  
282X X X  X X XX X X     0011 1000 2 SEC       72                                  
283X  XX X  XX X  X  X   1001 0010 4 STA (a8),Z                               27          
284X X X  X XX X X X     0001 1000 2 CLC     74                                    
285X X  X X X X X X    X 1111 1100 6 PHW a16   54                         24 27          
286X X  X X X X X X     X1111 1100 7 PHW a16                     44        26           
287X X  XX  X X X X X    1111 0100 3 PHW #d16                     44                    
288X X  X X X X X X   X  1111 1100 5 PHW a16 32                   44                    


ROM output signals description

Following table shows ROM output signals and their meaning. There are 76 different signals. Note that each ROM output signal goes high during P1 of corresponding cycle. Then it goes thru one or more flip flops which prolong it to two P phases and delay it, and thus it becomes control signal.
Sometimes where there is too much OR terms for a ROM output signal the resulting signal gets ORed from two subsignals. Signals 16 and 17 or 25 and 26 are such examples. Such pairs have the same color in above table.
When there is simple number in SIG # column the ROM output signal is delayed by one clock phase (half cycle). So for example signal 25 (together with 26) generates one ROM output signal. Let's have PHA instruction. It gets loaded into instruction register during T1P2. During T3P1 combination of signals 25 and 26 goes high. Then it is delayed and prolonged by one half cycle so the resulting control signal ROMSYNC is active during T3P2 and T4P1. In fact it is delayed once more at the SYNC pin by one clock phase so that SYNC signal goes high at T4P1 and T4P2 which is in fact T1P1 and T1P2 of the next instruction.
When there is a minus sign attached to the number in SIG # column it means that the corresponding ROM output control signal is not delayed at all, it is just prolonged by one half cycle. Again we look at the PHA instruction. Here signal 27- gets high at T2P1. The resulting output signal ROMWR goes high at T2P1 and T2P2. Again this signal is delayed at the R/W pin by two clock phases (whole cycle) so that R/W pin goes down at T3P1 and T3P2.
When there is a plus sign attached to the number in SIG # column it means that the corresponding ROM output control signal is delayed by two clock phases (whole cycle) and of course prolonged by one clock phase too. In PHA instruction, the ROM output signal 24+ gets high at T2P1. Resulting control signal ROMSPOUT goes high at T3P1 and T3P2. This signal causes that instead of PC the content of the SP is transferred to the address bus.
Table with above mentioned info is given just below, the table with the ROM output signals is given below it.

The table below shows the three different delays of ROM output signals. The table shows example of PHA instruction. There are three sections. First, the yellow one, shows delay by one clock phase. The name of the signals are given in their full form, i.e. ROMOUTxx without possible "+" or "-" at the end, exactly how those signals are shown in the schematic. The first cycle is named Tx/T1 as 65CE02 has fetch/execute overlap as many similar CPUs. So the T1 of every instruction is in the same time last cycle of previous instruction. At T1P1 IR contains "xx" as it is arbitrary previous instruction. ROMSYNC has unknown value as well as a high value at SYNC pad could be triggered not only by ROMSYNC signal, but as well by PRESYNC signal which goes high for simple instructions one cycle long (i.e. NOP, TAX). The green part shows the no delay option, marked by "-" at the end of signal numbers in the table below. The red part shows a delay by two clock phases marked by "+" at the end of signal numbers in the table below. PRG pad is a pad located between A7 pad and A8 pad. It is not connected to any outside pin of 65CE02. It is high when there is PC register on the address bus. It is low when there is SP, AB or AD registers there.

TxPxIRnothing-+
ROMOUT25ROMSYNCSYNC PADROMOUT27ROMWRR/W PADROMOUT24SPOUTPRG PAD
Tx/T1P1xx0x1001001
P2DA001001001
T2P1DA000111101
P2DA000011001
T3P1DA100000010
P2DA010000010
T4/T1P1DA011001001
P2xx001001001


Table below shows the list of ROM output signals. Note that real signals in schematic have names like ROMOUTxx where xx is the number of the signal. Column D (Delay) shows how much is the signal delayed before goes to its target place. Nothing (empty cell) means it is delayed by one clock phase, "+" means by two whereas "-" means no delay at all. Besides the delay the ROM output signal is prolonged by one clock phase so it is two phases long. See table above. If there is "*" in P1 column the prolonged signal is shortened so it occurs in P1 only. This happens only when a register should be modified - written to, incremented, etc. Not every register uses this feature, for example B, DIN, DOUT don't. Column O (Output) shows if output signal is normal (cell empty), inverted ("/") or both normal and inverted ("X").
Some control signals don't go from ROM but are derived from another ROM output signals. For example ALUORA = NOR(ALUSHL, ALUSHR, ALUADD, ALUAND, ALUEOR), i.e. when ALU is not being asked to perform any other function, it performs OR. Transfering register to register is done via ALU which performes OR with zero byte.
Another example is PC2Ax = NOR(ROMSPOUT, ROMADOUT, ROMABOUT). When no other register pair is asked to go out to address bus (SP, AD, AB), the PC is automatically presented there.
Or - RDDIN = NOR(ROMRDA, ROMRDB, ROMRDX, ROMRDY, ROMRDZ, READFLAGS, ROMRDPCH, ROMRDPCL, ROMRDSPH, ROMRDSPL, GETVECT), if no other register is read to REGBUS (which is one of the sources of ALU), DIN register is automatically read. DIN register contains last value read from data bus, which is read every P2 of each cycle which does not writes a value out from the CPU. I.e. signal WRDIN = NOR(W/R, P1a, P1b). W/R is derived from ROMWR, and R/W pad value is derived from W/R by slight delay and negation. P1a and P1b are internal P1 signals. P1b is slightly delayed P1a. Both of them in that NOR formula shorten WRDIN signal little bit.
Sometimes ROM out signal has to be mixed with some condition. For example DECCOR = AND(ALUADCINS, FLAGD). Decadic correction takes place only when ADC or SBC instruction is being executed and when flag D is on (FLAGD).
Or - WRSPH = AND(AND(ROMWRSPH, OR(ROMRDY, /FLAGE)), NOT(P2a)), real writing to SPH occurs at P1 (taken here as negation of P2a), when /FLAGE is on, i.e. stack extend enabled or register Y is just being read, i.e. TYS instruction writes to SPH regardles of the E flag.
Or - WRPCL = AND(ROMWRPCL, CONDMET, NOT(P2a)), real writing to PCL occurs at P1 (again taken here as negation of P2a) and when CONDMET signal is on. CONDMET is always on with the exception when the condition code (flag) is examined and the condition is false. So the writing does not take place in conditional branches when the condition is false for example.

00   ROMRDBreads from register B
01 * ROMWRABHwrites to register ABH
02   ROMWRBwrites to register B
03 */INHABHINCinhibits incrementing of ABH (a8),Z; (a8,X); (a8),Y, INW/DEW a8
04 * ROMWRADHwrites to register ADH
05+  ROMADOUTindirect addres to address bus
06 * ROMWRSPHwrites to register SPH (high half of SP)
07   GETVECTgets vector for BRK
08 * ROMWRABwrites to register ABL and copies B to ABH
09 * ADJPCHadjusts PCH if necessary (CY or BR from PCL)
10 * ROMWRPCHwrites to PCL (from ALUEA)
11   CINONEsets carry in to 1 (INC, CMP, ...)
12   CINFLAGCputs flag C into carry in
13   CINDLDCputs delayed C into carry in (16 bit operation)
14  XALUSHLshift left (ASL, ROL)
15  XALUSHRshift left (ASR, LSR, ROR)
16,17  XALUADDall adding from ALU, i.e. ADC/SBC instruction and effective address calculation
18  /ROMWORDZZ flag for words (INW, DEW, ASW, ROW)
19  XALUANDperforms AND
20  XALUEORperforms EOR
21   ROMRDPCHreads to register PCH (high half of PC)
22   NOTALUAgets NOT A for TRB
23   ALUADCINSperforms ADC (both binary and decimal), i.e. instruction itself
24+  ROMSPOUTstack to address bus
25,26  /ROMSYNCsync pad
27-  ROMWRwrite pad
28,29   GETALUBgets alu B, if not bit is generated or alu B is 0
30   GENBITgenerates bit from b4b5b6
31 * ROMINCABincrements AB counter
32+  ROMABOUTeffective address to address bus
33 * ROMWRADLwrites to register ADL
34,35  XMODFLAGZmodifies flag Z (TBA, ORA, AND, ...)
36,37  XMODFLAGNmodifies flag N (ASL, ROL, LDZ, PLZ, TAZ, ASW, ROW, AND, ADC, LDA, SBC, LSR, ROR, ...)
38   NOTALUBnegates ALU B
39   ROMRDSPHreads from register SPH (low half of SP)
40   INHPCINCinhibits incrementing of PC during the inactive bus cycles
41 * ROMADL2PCLcopies ADL to PCL
42 * ROMWRPCLwrites to PCL (from ALUEA)
43   ROMRDPCLreads to register PCL (low half of PC)
44 * ROMDECSPdecrements SP (JSR, PHA, ...)
45 * ROMINCSPincrements SP (RTS, PLA, ...)
46 * ROMWRSPLwrites to register SPL (low half of SP)
47   ROMRDSPLreads from register SPL (low half of SP)
48   ROMRDZreads from register Z
49 * ROMWRZwrites to register Z
50   ROMRDYreads from register Y
51 * ROMWRAwrites to register A
52 * ROMWRYwrites to register Y
53   ROMRDXreads from register X
54   ROMWRDOUTwrites to DOUT register
55 * ROMWRXwrites to register X
56   ROMRDAreads from register A
57- XBBSRxinstructions BBR0 - BBR7, BBS0 - BBS7
58- XTESTFLAGZtests flag Z (BNE, BEQ)
59- XTESTFLAGNtests flag N (BPL, BMI)
60- XONFLAG0branches if flag is 0 (BBS, BPL, BVC, BCC, BNE)
61- XTESTFLAGVtests flag V (BVC, BVS)
62+ XMODFLAGVmodifies flag V (ADC, SBC, BIT)
63-  CLRFLAGVclears flag V (CLV)
64-  SETFLAGIsets flag I (SEI)
65-  CLRFLAGIclears flag I (CLI)
66-  SETFLAGEsets flag E (SEE)
67-  CLRFLAGEclears flag E (CLE)
68-  SETFLAGDsets flag D (SED)
69-  CLRFLAGDclears flag D (CLD)
70+  READFLAGSreads flags (BRK, PHP)
71- XTESTFLAGCtests flag C (BCC, BCS, BLS)
72-  SETFLAGCsets flag C (SEC)
73+ XMODFLAGCmodifies flag C (ADC, SBC, CMP, CPX, CPY, CPZ, ASL, ROL, ASW, ROW, ASR, LSR, ROR)
74-  CLRFLAGCclears falg C (CLC)
75+ XWRITEFLAGSwrites flags (RTI, PLP)